双极晶体管混合传输晶体管逻辑
Hybrid Pass Transistor Logic with Ambipolar Transistors
摘要：
与传统的互补上拉和下拉逻辑结构相比，传输晶体管逻辑（PTL）系列减少了执行逻辑功能所需的晶体管的数量，从而减少了面积和功耗。然而，该逻辑系列需要级间反相器以确保级联逻辑电路中的信号完整性，并且反相器必须用于以其互补形式提供每个逻辑输入信号。这些反相器和互补信号增加了器件数量，并显著降低了整体系统效率。双栅极双极性场效应晶体管本身提供单晶体管XNOR操作，并且由于其双极性能力而允许高效和紧凑的电路。类似于PTL，基于双极性场效应晶体管的逻辑电路需要互补信号。因此，需要大量的逆变器，具有显著的能量和面积成本。双极性场效应晶体管是PTL的天然匹配，因为混合双极性PTL电路可以同时使用这些反相器来满足PTL和双极性电路中的需要。因此，我们提出了一种新的混合双极PTL逻辑家庭，利用紧凑的逻辑PTL和双极型场效应晶体管的双极能力。新型混合双极性PTL电路的设计和SPICE仿真，展示了强大的信号完整性以及使用所需的反相器，以同时满足PTL和双极性电路的要求的效率优势。与传统CMOS逻辑结构中的双极性场效应晶体管相比，我们的混合全加器电路可以将传播延迟减少47%，能量消耗减少88%，能量延迟积减少9倍，面积能量延迟积减少20倍。
英文摘要：
In comparison to the conventional complementary pull-up and pull-down logic structure, the pass transistor logic (PTL) family reduces the number of transistors required to perform logic functions, thereby reducing both area and power consumption. However, this logic family requires inter-stage inverters to ensure signal integrity in cascaded logic circuits, and inverters must be used to provide each logical input signal in its complementary form. These inverters and complementary signals increase the device count and significantly degrade overall system efficiency. Dual-gate ambipolar field-effect transistors natively provide a single-transistor XNOR operation and permit highly-efficient and compact circuits due to their ambipolar capabilities. Similar to PTL, logic circuits based on ambipolar field-effect transistors require complementary signals. Therefore, numerous inverters are required, with significant energy and area costs. Ambipolar field-effect transistors are a natural match for PTL, as hybrid ambipolar-PTL circuits can simultaneously use these inverters to satisfy their necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional CMOS logic structure, our hybrid full adder circuit can reduce propagation delay by 47%, energy consumption by 88%, energy-delay product by a factor of 9, and area-energy-delay product by a factor of 20.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
