利用RapidWright自动生成专用FPGA覆盖图
Exploiting RapidWright in the Automatic Generation of Application-Specific FPGA Overlays
摘要：
在FPGA器件上实现的覆盖架构已被提出作为增加FPGA在通用计算中采用的一种手段。它们提供了软件的好处，如灵活性和可编程性，从而使构建专用编译器变得更容易。然而，现有的覆盖是通用的，资源和功率消耗大，性能通常比裸金属实现低一个数量级。因此，FPGA覆盖一直局限于研究和一些利基应用。在本文中，我们介绍了专用FPGA覆盖层（AS-覆盖层），它可以为FPGA覆盖层提供裸金属性能，从而为更广泛的采用打开大门。我们的方法是基于自动提取的硬件内核从数据流应用程序。提取的内核然后被用于硬件加速器的特定于应用的生成。覆盖的重新配置是用RapidWright完成的，它允许绕过HDL设计流程。通过原型设计，我们证明了我们的方法的可行性和相关性。实验表明，与最先进的FPGA叠加相比，生产率提高了20倍，同时实现了比直接FPGA实现高出1.33倍的Fmax，并且与裸金属相比，资源和功耗更低。
英文摘要：
Overlay architectures implemented on FPGA devices have been proposed as a means to increase FPGA adoption in general-purpose computing. They provide the benefits of software such as flexibility and programmability, thus making it easier to build dedicated compilers. However, existing overlays are generic, resource and power hungry with performance usually an order of magnitude lower than bare metal implementations. As a result, FPGA overlays have been confined to research and some niche applications. In this paper, we introduce Application-Specific FPGA Overlays (AS-Overlays), which can provide bare-metal performance to FPGA overlays, thus opening doors for broader adoption. Our approach is based on the automatic extraction of hardware kernels from data flow applications. Extracted kernels are then leveraged for application-specific generation of hardware accelerators. Reconfiguration of the overlay is done with RapidWright which allows to bypass the HDL design flow. Through prototyping, we demonstrated the viability and relevance of our approach. Experiments show a productivity improvement up to 20x compared to the state of the art FPGA overlays, while achieving over 1.33x higher Fmax than direct FPGA implementation and the possibility of lower resource and power consumption compared to bare metal.
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