IMAGine：一种内存加速的GEMV引擎覆盖架构
IMAGine: An In-Memory Accelerated GEMV Engine Overlay
AI总结：
针对现有FPGA基PIM架构时钟低、扩展差的问题，提出可满频运行、全占BRAM的IMAGine GEMV加速器，其时钟速度、MAC单元规模优于同类方案及多款商用AI芯片。
摘要：
为消除冯·诺依曼瓶颈并使处理性能随BRAM（块随机存取存储器）容量扩展，学界已提出内存内处理（PIM）覆盖架构与全新重新设计的可重构瓦片阵列结构。但这类基于FPGA的PIM架构性能受限，原因是BRAM最高时钟频率降低，且处理单元随BRAM容量增加的扩展效果未达理想水平。\n本文提出IMAGine——一款内存加速GEMV（通用矩阵向量乘）引擎，它是一种PIM阵列加速器，可在BRAM最高频率下运行，且能扩展至占用全部可用BRAM的100%。对比分析显示，其执行速度优于现有FPGA上基于PIM的GEMV引擎，时钟速度提升2.65倍至3.2倍。\n在AMD Alveo U55上的实现方案达成了737MHz的系统时钟频率，可提供64K个位串行乘累加（MAC）单元用于GEMV运算。这确立了IMAGine作为最快的基于PIM的GEMV覆盖架构的地位，性能甚至超过迄今已报道的定制化基于PIM的FPGA加速器。此外，它的时钟速度超过TPU v1-v2与阿里含光800，同时提供数量相当或更多的MAC单元。
英文摘要：
Processor-in-Memory (PIM) overlays and new redesigned reconfigurable tile fabrics have been proposed to eliminate the von Neumann bottleneck and enable processing performance to scale with BRAM capacity. The performance of these FPGA-based PIM architectures has been limited due to a reduction of the BRAMs maximum clock frequencies and less than ideal scaling of processing elements with increased BRAM capacity. This paper presents IMAGine, an In-Memory Accelerated GEMV engine, a PIM-array accelerator that clocks at the maximum frequency of the BRAM and scales to 100% of the available BRAMs. Comparative analyses are presented showing execution speeds over existing PIM-based GEMV engines on FPGAs and achieving a 2.65x - 3.2x faster clock. An AMD Alveo U55 implementation is presented that achieves a system clock speed of 737 MHz, providing 64K bit-serial multiply-accumulate (MAC) units for GEMV operation. This establishes IMAGine as the fastest PIM-based GEMV overlay, outperforming even the custom PIM-based FPGA accelerators reported to date. Additionally, it surpasses TPU v1-v2 and Alibaba Hanguang 800 in clock speed while offering an equal or greater number of MAC units.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
