异构三维SoCs中的NoCs：布线策略和微架构的协同设计
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures
摘要：
异构3D片上系统（3D SoC）是将传感和计算结合在单个芯片内的最有前途的设计范例。异构3D SoC中的通信网络的一个特殊特性是每层中的不同延迟和吞吐量。正如这项工作所示，这种变化大大降低了网络性能。我们贡献的路由算法和路由器微架构，可以克服这些性能限制的共同设计。我们分析了异质性的挑战：提出了技术感知的通信模型，从而确定数据包传输速度较慢的层。通信模型对于零负载下的延迟和吞吐量是精确的。该技术模型对于90至28 nm的各种商业技术具有小于7.4%的面积误差和时序误差。其次，我们展示了如何克服异质性的限制，提出了两种新的路由算法，称为Z+（XY）Z-和ZXYZ，提高延迟高达6.5倍相比，传统的尺寸顺序路由。此外，我们提出了一个高的垂直吞吐量路由器的微架构，调整到路由算法，并充分克服了较慢的层的限制。与传统路由器相比，我们实现了2到4倍的吞吐量增加。因此，路由器的动态功率降低了高达41.1%，我们实现了高达2.26倍的改进微片延迟，在2.1%和10.4%之间的小总路由器面积成本为现实的技术和应用场景。
英文摘要：
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication networks in heterogeneous 3D SoCs is the varying latency and throughput in each layer. As shown in this work, this variance drastically degrades the network performance. We contribute a co-design of routing algorithms and router microarchitecture that allows to overcome these performance limitations. We analyze the challenges of heterogeneity: Technology-aware models are proposed for communication and thereby identify layers in which packets are transmitted slower. The communication models are precise for latency and throughput under zero load. The technology model has an area error and a timing error of less than 7.4% for various commercial technologies from 90 to 28nm. Second, we demonstrate how to overcome limitations of heterogeneity by proposing two novel routing algorithms called Z+(XY)Z- and ZXYZ that enhance latency by up to 6.5x compared to conventional dimension order routing. Furthermore, we propose a high vertical-throughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers. We achieve an increased throughput of 2 to 4x compared to a conventional router. Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieve improved flit latency of up to 2.26x at small total router area costs between 2.1% and 10.4% for realistic technologies and application scenarios.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
