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arXiv 1907.08641cs.AR
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PPAC:一个多功能的内存中矩阵向量积类运算加速器

PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations

Oscar Castañeda, Maria Bobbett, Alexandra Gallyas-Sanhueza, Christoph Studer

摘要:

内存中处理(PIM)将计算移动到内存中,与传统的基于冯诺依曼的架构相比,其目标是提高吞吐量和能效。大多数现有的PIM架构要么是通用的,但只支持原子操作,或专门用于加速单个任务。我们提出了关联内容可寻址存储器(PPAC)中的并行处理器,这是一种新型的内存加速器,支持一系列类似于矩阵向量积(MVP)的操作,可用于传统和新兴应用。例如,PPAC能够加速低精度神经网络、精确/近似散列查找、加密和前向纠错。PPAC的全数字特性使其能够使用基于标准单元的CMOS实现,这有助于自动化设计和技术节点之间的可移植性。为了证明PPAC的有效性,我们提供了不同阵列尺寸的28 nm CMOS布局后实施结果。与最近的数字和混合信号PIM加速器的比较表明,PPAC在吞吐量和能效方面具有竞争力,同时加速了广泛的应用并简化了开发。

英文摘要:

Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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