在gem5中集成DRAM省电模式并量化其影响
Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact
摘要：
在各种应用中，DRAM是整个系统功耗的重要贡献者，与片上存储器访问相比，DRAM每比特访问能量高出三个数量级。为了提高功率效率，DRAM技术结合了多种掉电模式，每种模式在可实现的功率节省与由于进入和退出延迟要求而导致的性能影响之间具有不同的权衡。这些低功耗模式以及进入和退出控制的准确建模对于分析具有不同存储器访问特性的控制器配置和工作负载之间的权衡至关重要。为了解决这个问题，我们将掉电模式集成到开源模拟器gem 5中的DRAM控制器模型中。这是第一个公开提供的具有DRAM掉电模式的全系统模拟器，为研究社区提供了一个用于广泛用例的DRAM功耗分析工具。我们验证的掉电功能与扫描测试，触发定义的内存访问特性。我们进一步评估模型与真正的HPC工作负载，说明低功耗功能集成到一个完整的系统模拟器的价值。
英文摘要：
Across applications, DRAM is a significant contributor to the overall system power, with the DRAM access energy per bit up to three orders of magnitude higher compared to on-chip memory accesses. To improve the power efficiency, DRAM technology incorporates multiple power-down modes, each with different trade-offs between achievable power savings and performance impact due to entry and exit delay requirements. Accurate modeling of these low power modes and entry and exit control is crucial to analyze the trade-offs across controller configurations and workloads with varied memory access characteristics. To address this, we integrate the power-down modes into the DRAM controller model in the open-source simulator gem5. This is the first publicly available full-system simulator with DRAM power-down modes, providing the research community a tool for DRAM power analysis for a breadth of use cases. We validate the power-down functionality with sweep tests, which trigger defined memory access characteristics. We further evaluate the model with real HPC workloads, illustrating the value of integrating low power functionality into a full system simulator.
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