用于MLC的极性编码前向纠错NAND闪存用于NAND闪存的极性FEC
Polar-Coded Forward Error Correction for MLC NAND Flash Memory Polar FEC for NAND Flash Memory
摘要:
随着存储密度的不断增长、数据存取的高速化和低成本化,闪存不可避免地变得流行起来。多级单元(MLC)NAND闪存能够很好地平衡数据密度和存储稳定性,占据了闪存的最大市场份额。然而,随着存储器规模的不断扩大,由于多种干扰,可靠性急剧下降。因此,控制系统应嵌入适当的纠错码(ECC),以保证数据的完整性和准确性。我们提出了预校验方案,这是一种多策略极化码方案,以在合理的帧出错率(FER)和解码延迟之间取得平衡。三个解码器,即二进制输入,量化软,和纯软解码器嵌入在该方案中。由于软对数似然比(LLR)输入的计算需要多个感测操作和可选的量化边界,提出了一种2比特量化的硬判决解码器,以更少的感测操作优于硬解码的LDPC比特翻转解码器。我们注意到,与LDPC码相比,极化码具有低得多的计算复杂性。提出了逐步最大互信息(SMMI)方法,在不穷尽搜索的情况下获得重叠边界。使用格雷码的映射方案,并证明了实现更好的原始错误性能相比,其他替代品。文中还给出了系统的硬件结构。
英文摘要:
With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied the largest market share of flash memory. With the aggressive memory scaling, however, the reliability decays sharply owing to multiple interferences. Therefore, the control system should be embedded with a suitable error correction code (ECC) to guarantee the data integrity and accuracy. We proposed the pre-check scheme which is a multi-strategy polar code scheme to strike a balance between reasonable frame error rate (FER) and decoding latency. Three decoders namely binary-input, quantized-soft, and pure-soft decoders are embedded in this scheme. Since the calculation of soft log-likelihood ratio (LLR) inputs needs multiple sensing operations and optional quantization boundaries, a 2-bit quantized hard-decision decoder is proposed to outperform the hard-decoded LDPC bit-flipping decoder with fewer sensing operations. We notice that polar codes have much lower computational complexity compared to LDPC codes. The stepwise maximum mutual information (SMMI) scheme is also proposed to obtain overlapped boundaries without exhausting search. The mapping scheme using Gray code is employed and proved to achieve better raw error performance compared to other alternatives. Hardware architectures are also given in this paper.
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