多尺度神经形态硬件集群的关键技术--全晶圆重分布和晶圆嵌入
Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster
摘要：
Fraunhofer IZM与Kirchhoff物理研究所（KIP）一起开发了一种完整的晶圆再分配和嵌入技术，作为大规模神经形态硬件系统的基础。本文将概述KIP的类脑计算平台以及推动所述技术发展的相关硬件要求。在项目的第一阶段，采用了晶圆级封装的标准再分配技术，以在200 mm CMOS晶圆上实现高密度的网线到网线布线。相邻的互连线通过基于半加成铜金属化的8μm间距布线跨越划线互连。通过光敏苯并环丁烯的钝化用于实现第二光罩内布线层。在每个掩模版的顶部生成具有闪光金的最终IO焊盘。有了这个概念，基于全晶片的神经形态系统就可以组装和测试。所制造的高密度中间掩模版布线显示出大于99.9%的非常高的成品率。为了使系统尺寸能够通过可行的努力扩大到大量晶片，在项目的第二阶段开发并证明了印刷电路板的全晶片嵌入概念。将晶片减薄至250μm，并与额外的预浸料层和铜箔层压成芯材料。在PCB板层压之后，通过微通孔钻孔、铜电镀、光刻和PCB布线结构的减蚀来访问嵌入式晶片的掩模版IO。所创建的具有50 μ m行宽的布线使得能够访问嵌入式晶片上的掩模版10以及板级布线。具有嵌入式晶片的面板随后在0 ° C和100 ° C之间用多达1000次热循环施加应力，并且在循环时间内没有显示出严重的失效形成。
英文摘要：
Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a high density reticle-to-reticle routing on 200mm CMOS wafers. Neighboring reticles were interconnected across the scribe lines with an 8μm pitch routing based on semi-additive copper metallization. Passivation by photo sensitive benzocyclobutene was used to enable a second intra-reticle routing layer. Final IO pads with flash gold were generated on top of each reticle. With that concept neuromorphic systems based on full wafers could be assembled and tested. The fabricated high density inter-reticle routing revealed a very high yield of larger than 99.9%. In order to allow an upscaling of the system size to a large number of wafers with feasible effort a full wafer embedding concept for printed circuit boards was developed and proven in the second phase of the project. The wafers were thinned to 250μm and laminated with additional prepreg layers and copper foils into a core material. After lamination of the PCB panel the reticle IOs of the embedded wafer were accessed by micro via drilling, copper electroplating, lithography and subtractive etching of the PCB wiring structure. The created wiring with 50um line width enabled an access of the reticle IOs on the embedded wafer as well as a board level routing. The panels with the embedded wafers were subsequently stressed with up to 1000 thermal cycles between 0C and 100C and have shown no severe failure formation over the cycle time.
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