基于Benes的混合关键嵌入式系统NoC交换结构
A Benes Based NoC Switching Architecture for Mixed Criticality Embedded Systems
摘要：
多核、混合关键性嵌入式（MCE）实时系统需要高的定时精度和可预测性，以保证任务之间没有干扰。这些保证在航空电子和汽车等应用领域是必要的，在这些领域，任务干扰或错过最后期限可能是灾难性的，并且安全要求非常严格。在现代多核系统中，互连成为一个潜在的不确定性点，在证明行为始终在指定的约束范围内时引入了重大挑战，限制了增加系统性能以增加更多任务或为现有任务提供更多计算资源的手段。我们提出MCENoC，片上网络（NoC）交换架构，提供创新，以克服这一可预测的，正式验证的时序行为，是一致的整个NoC。我们展示了Benes网络的基本特性如何使MCE应用受益，并满足我们的架构要求。使用SystemVerilog断言（SVA），正式属性的定义，帮助细化的设计规范，以及使实现进行详尽的正式验证。我们展示了设计的大小，吞吐量和可预测性方面的性能，并讨论了利用这种架构所需的应用程序级别的考虑因素。
英文摘要：
Multi-core, Mixed Criticality Embedded (MCE) real-time systems require high timing precision and predictability to guarantee there will be no interference between tasks. These guarantees are necessary in application areas such as avionics and automotive, where task interference or missed deadlines could be catastrophic, and safety requirements are strict. In modern multi-core systems, the interconnect becomes a potential point of uncertainty, introducing major challenges in proving behaviour is always within specified constraints, limiting the means of growing system performance to add more tasks, or provide more computational resources to existing tasks. We present MCENoC, a Network-on-Chip (NoC) switching architecture that provides innovations to overcome this with predictable, formally verifiable timing behaviour that is consistent across the whole NoC. We show how the fundamental properties of Benes networks benefit MCE applications and meet our architecture requirements. Using SystemVerilog Assertions (SVA), formal properties are defined that aid the refinement of the specification of the design as well as enabling the implementation to be exhaustively formally verified. We demonstrate the performance of the design in terms of size, throughput and predictability, and discuss the application level considerations needed to exploit this architecture.
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