Calipers：一个关键度感知的处理器性能建模框架
Calipers: A Criticality-aware Framework for Modeling Processor Performance
摘要：
计算机体系结构设计空间广阔而复杂。需要工具来探索新的想法，并快速获得见解，以较低的努力和所需的准确性。我们提出卡尺，一个基于关键性的框架来模拟复杂体系结构的关键抽象和程序的执行使用动态事件依赖图。通过应用图形算法，Calipers可以跟踪指令和事件依赖性，计算关键路线，并分析架构瓶颈。通过操作图形，Calipers使架构师能够在早期和后期设计空间探索期间调查广泛的指令集架构（ISA）和微架构设计选择/“假设”场景，而无需重新编译和重新运行程序。卡尺可以对有序和无序的微架构、结构风险和不同类型的ISA进行建模，并且可以在一次运行中评估多个想法。详细描述了建模算法。我们应用Calipers来探索和深入了解RISC和EDGE处理器的复杂微架构和ISA思想，其工作量低于周期精确的模拟器，并且具有相当的精度。例如，在本文提出的各种调查中，实验表明，仅针对一小部分关键负载可以帮助实现价值预测的大部分好处。
英文摘要：
Computer architecture design space is vast and complex. Tools are needed to explore new ideas and gain insights quickly, with low efforts and at a desired accuracy. We propose Calipers, a criticality-based framework to model key abstractions of complex architectures and a program's execution using dynamic event-dependence graphs. By applying graph algorithms, Calipers can track instruction and event dependencies, compute critical paths, and analyze architecture bottlenecks. By manipulating the graph, Calipers enables architects to investigate a wide range of Instruction Set Architecture (ISA) and microarchitecture design choices/"what-if" scenarios during both early- and late-stage design space exploration without recompiling and rerunning the program. Calipers can model in-order and out-of-order microarchitectures, structural hazards, and different types of ISAs, and can evaluate multiple ideas in a single run. Modeling algorithms are described in detail. We apply Calipers to explore and gain insights in complex microarchitectural and ISA ideas for RISC and EDGE processors, at lower effort than cycle-accurate simulators and with comparable accuracy. For example, among a variety of investigations presented in the paper, experiments show that targeting only a fraction of critical loads can help realize most benefits of value prediction.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
