关键性感知多处理器
Criticality Aware Multiprocessors
摘要：
通常，来自处理器的存储器请求在其最终被服务之前可能需要经过许多中间互连路由器、目录节点、所有者节点等。当前的多处理器不优先考虑任何特定的存储器请求。但是某些内存请求对多处理器的性能比其他请求更重要。范例：来自关键部分的存储器请求、馈送到多个相关指令中的加载请求等。通过让排序点和互连路由器将关键请求优先于非关键请求，该知识可用于改进当前多处理器的性能。在本文中，我们使用SIMICS/GEMS基础设施进行评估。对于锁密集型微基准测试，临界感知多处理器显示出比基线多处理器提高5-15%的性能。关键性感知多处理器为挖掘共享内存多处理器的性能提供了一个新的方向，并且可以在锁密集型基准测试中提供实质性的加速。
英文摘要：
Typically, a memory request from a processor may need to go through many intermediate interconnect routers, directory node, owner node, etc before it is finally serviced. Current multiprocessors do not give preference to any particular memory request. But certain memory requests are more critical to multiprocessor's performance than other requests. Example: memory requests from critical sections, load request feeding into multiple dependent instructions, etc. This knowledge can be used to improve the performance of current multiprocessors by letting the ordering point and the interconnect routers prioritize critical requests over non-critical ones. In this paper, we evaluate using SIMICS/GEMS infrastructure. For lock-intensive microbenchmarks, criticality-aware multiprocessors showed 5-15% performance improvement over baseline multiprocessor. Criticality aware multiprocessor provides a new direction for tapping performance in a shared memory multiprocessor and can provide substantial speedup in lock intensive benchmarks.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
