加密MIPS处理器的高效硬件设计与实现
Efficient Hardware Design and Implementation of Encrypted MIPS Processor
摘要：
介绍了基于MIPS流水线结构的32位加密MIPS处理器的设计和硬件实现。流水线级的组织方式，使流水线能够以高频率计时。借助框图，详细说明了数据加密标准（DES）密码体制的加、解密模块及其相互间的依赖关系。为了增加处理器的功能和性能，特别是对于安全应用，我们包括三个新的指令32位LKLW，LKUW和CMPT。该设计已综合在40纳米工艺技术的目标使用Xilinx Virtex-6设备。该加密MIPS流水线处理器在合成级可以工作在218 MHz，在模拟级可以工作在744 MHz。
英文摘要：
The paper describes the design and hardware implementation of 32-bit encrypted MIPS processor based on MIPS pipeline architecture. The organization of pipeline stages in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of data encryption standard (DES) cryptosystem and dependency among themselves are explained in detail with the help of block diagram. In order to increase the processor functionality and performance, especially for security applications we include three new instructions 32-bit LKLW, LKUW and CRYPT. The design has been synthesized at 40nm process technology targeting using Xilinx Virtex-6 device. The encrypted MIPS pipeline processor can work at 218MHz at synthesis level and 744MHz at simulation level.
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