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arXiv 1306.1916cs.CRcs.AR
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基于密码算法的低功耗MIPS密码处理器性能评估

Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms

Kirat Pal Singh, Dilip Kumar

摘要:

本文介绍了一种基于MIPS流水线结构的低功耗32位加解密处理器的设计与实现,该处理器可对数据加密标准(DES)、三重DES、高级加密标准(AES)进行加解密。流水线阶段的组织已经以这样一种方式完成,即流水线可以以高频率计时。本文用框图详细说明了MIPS处理器上三种标准密码算法的加、解密模块及其相互间的依赖关系。MIPS密码处理器采用门控时钟技术来降低功耗。这种方法导致处理器满足安全应用的功耗和性能规范。提出的实现方法包括更高的系统性能,同时降低操作功耗。测试结果表明,MIPS密码处理器工作频率为218 MHz,带宽为664 Mbits/s。

英文摘要:

This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed Implementation approach concludes higher system performance while reducing operating power consumption. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of 218MHz and a bandwidth of 664Mbits/s.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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