图像处理硬件加速器的自动优化
Automatic Optimization of Hardware Accelerators for Image Processing
摘要：
在图像处理领域，经常需要实时约束。特别是在安全关键型应用中，例如医学成像中的X射线计算机断层扫描或汽车领域中的高级驾驶员辅助系统，时序至关重要。维持计算密集型应用的实时能力的常见方法是将那些计算卸载到专用加速器硬件，诸如现场可编程门阵列（FPGA）。编程这样的架构是一项具有挑战性的任务，相对于典型的FPGA特定的设计标准：可扩展的整体算法延迟和FPGA原语（BRAM，FF，LUT和DSP）的资源使用。高级综合（HLS）通过使用著名的高级语言（C/C++）描述算法及其可由HLS工具完成的自动综合，极大地简化了这一任务。然而，算法开发人员仍然需要关于目标体系结构的专业知识，以实现令人满意的结果。因此，在以前的工作中，我们已经表明，提升图像算法的描述到一个更高的抽象层次，通过使用特定领域的语言（DSL），可以显着降低设计FPGA的算法的复杂性。为了让开发人员更好地控制常见的权衡，延迟与资源使用，我们将提出一个自动优化过程，其中这些标准被分析并反馈给DSL编译器，以生成更接近所需设计规范的代码。最后，我们生成立体块匹配算法的代码，并将其与手写实现进行比较，以量化我们的结果的质量。
英文摘要：
In the domain of image processing, often real-time constraints are required. In particular, in safety-critical applications, such as X-ray computed tomography in medical imaging or advanced driver assistance systems in the automotive domain, timing is of utmost importance. A common approach to maintain real-time capabilities of compute-intensive applications is to offload those computations to dedicated accelerator hardware, such as Field Programmable Gate Arrays (FPGAs). Programming such architectures is a challenging task, with respect to the typical FPGA-specific design criteria: Achievable overall algorithm latency and resource usage of FPGA primitives (BRAM, FF, LUT, and DSP). High-Level Synthesis (HLS) dramatically simplifies this task by enabling the description of algorithms in well-known higher languages (C/C++) and its automatic synthesis that can be accomplished by HLS tools. However, algorithm developers still need expert knowledge about the target architecture, in order to achieve satisfying results. Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs. To give the developer even more control over the common trade-off, latency vs. resource usage, we will present an automatic optimization process where these criteria are analyzed and fed back to the DSL compiler, in order to generate code that is closer to the desired design specifications. Finally, we generate code for stereo block matching algorithms and compare it with handwritten implementations to quantify the quality of our results.
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