具有时间敏感仿射类型的可预测加速器设计
Predictable Accelerator Design with Time-Sensitive Affine Types
摘要：
现场可编程门阵列（FPGA）提供了一个与硬件加速器共同设计应用程序的机会，但它们仍然很难编程。高级综合（HLS）工具承诺通过将C或C++编译为加速器设计来提高抽象级别。然而，重新使用遗留软件语言需要复杂的逻辑来将命令式代码映射到硬件结构上。我们发现HLS中的黑盒算法可能是不可预测的：改变程序中的参数来提高性能可能会违反直觉地产生更慢和更大的设计。本文提出了一种类型系统，限制HLS的程序，可以预测编译到硬件加速器。其核心思想是用一个对时间敏感的仿射型系统来模拟可消耗的硬件资源，该系统可以防止同时使用相同的硬件结构。我们实现的类型系统在大丽花，编译到HLS C++的语言，并表明它可以减少HLS参数空间的大小，同时接受帕累托最优设计。
英文摘要：
Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures. We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a language that compiles to HLS C++, and show that it can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
