Processing data received as a stream is a task commonly performed by modern embedded devices, in a wide range of applications such as multimedia (encoding/decoding/ playing media), networking (switching and routing), digital security, scientific data processing, etc. Such processing normally tends to be calculation intensive and therefore requiring significant processing power. Therefore, hardware acceleration methods to increase the performance of such applications constitute an important area of study. In this paper, we present an evaluation of one such method to process streaming data, namely multi-processor pipeline architecture. The hardware is based on a Multiple-Processor System on Chip (MPSoC), using a data encryption algorithm as a case study. The algorithm is partitioned on a coarse grained level and mapped on to an MPSoC with five processor cores in a pipeline, using specifically configured Xtensa LX3 cores. The system is then selectively optimized by strengthening and pruning the resources of each processor core. The optimized system is evaluated and compared against an optimal single-processor System on Chip (SoC) for the same application. The multiple-processor pipeline system for data encryption algorithms used was observed to provide significant speed ups, up to 4.45 times that of the single-processor system, which is close to the ideal speed up from a five-stage pipeline.
PEEK: Heterogeneous Parallelism for Privileged Error Detection in Safety-Critical Processors
Southeast University, China（东南大学）；National Center of Technology Innovation for EDA, China（EDA技术创新国家中心）；National University of Defense Technology, China（国防科技大学）；New Jersey Institute of Technology, US（新泽理工学院）；University of Edinburgh, UK（爱丁堡大学）
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Computer Systems Lab, School of Engineering & Applied Sciences, Yale University（耶鲁大学工程与应用科学学院计算机系统实验室）；Center of Theoretical Neuroscience, Columbia University（哥伦比亚大学理论神经科学中心）；Institute of Neuroinformatics, University of Zurich and ETH Zurich（苏黎世大学与苏黎世联邦理工学院神经信息学研究所）
GFormer: Accelerating Large Language Models with Optimized Transformers on Gaudi Processors
University of Houston（休斯顿大学）；Indiana University（印第安纳大学）；Stevens Institute of Technology（史蒂文斯理工学院）；Argonne National Laboratory（阿贡国家实验室）；Binghamton University（宾汉姆顿大学）
