arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 1007.2131cs.LOcs.FL
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嵌入式系统设计验证中的等价性检查

Equivalence Checking in Embedded Systems Design Verification

S. Bandyopadhyay, D. Sarkar, C. R. Mandal

摘要:

在这份报告中,我们专注于嵌入式系统的建模和形式化验证相关的一些方面。已经提出了许多模型来表示嵌入式系统。这些模型涵盖了广泛的风格,特点和应用领域,包括有限状态机,数据流图,通信过程和Petri网的扩展。在本报告中,我们使用了PRES+模型(基于Petri网的嵌入式系统表示)作为经典Petri网模型的扩展,该模型捕获了嵌入式系统的并发性和时序行为;它允许系统在不同的抽象级别中具有代表性,并通过允许令牌携带信息来提高表达能力。如上所述,使用PRES+建模可能便于指定输入行为,因为它支持并发性。然而,据我们所知,文献中没有报道PRES+模型的等价性检查方法。相反,存在FSMD模型的等价性检查。作为第一步,因此,我们试图设计一个算法,将PRES+模型FSMD模型。

英文摘要:

In this report we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems. These models encompass a broad range of styles, characteristics, and application domains and include the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this report, we have used a PRES+ model (Petri net based Representation for Embedded Systems) as an extension of classical Petri net model that captures concurrency, timing behaviour of embedded systems; it allows systems to be representative in different levels of abstraction and improves expressiveness by allowing the token to carry information. Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concurrency. However, there is no equivalence checking method reported in the literature for PRES+ models to the best of our knowledge. In contrast, equivalence checking of FSMD models exist. As a first step, therefore, we seek to devise an algorithm to translate PRES+ models to FSMD models.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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