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arXiv 0710.4848cs.LO
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数据完整性的形式化验证方法

A Formal Verification Methodology for Checking Data Integrity

Yasushi Umezawa, Takeshi Shimizu

摘要:

形式化验证技术在预硅验证过程中发挥着重要作用。在进行形式化验证时考虑的最重要的一点是定义好的验证范围,我们应该明确定义在测试中的设计要正式验证什么。在定义形式化验证的范围时,我们考虑了以下三个实际需求。它们(a)难以核实(b)小到难以处理(c)容易理解。我们的新方法是将系统的通用属性分解为块级的原型属性,并定义可验证RTL的需求。因此,每个设计者而不是验证专家可以很容易地描述设计的属性,形式化的模型检验可以系统地和彻底地应用到所有的叶子模块。在服务器平台组件芯片的开发过程中,我们专注于RAS(可靠性,可用性和可服务性)功能,并在PSL中描述了2000多个属性。通过形式化验证,我们在有限的时间内发现了几个关键的逻辑错误,并成功地验证了所有这些错误。本文提出了一种功能验证方法的研究。

英文摘要:

Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verification is to define good verification scopes; we should define clearly what to be verified formally upon designs under tests. We considered the following three practical requirements when we defined the scope of formal verification. They are (a) hard to verify (b) small to handle, and (c) easy to understand. Our novel approach is to break down generic properties for system into stereotype properties in block level and to define requirements for Verifiable RTL. Consequently, each designer instead of verification experts can describe properties of the design easily, and formal model checking can be applied systematically and thoroughly to all the leaf modules. During the development of a component chip for server platforms, we focused on RAS (Reliability, Availability, and Serviceability) features and described more than 2000 properties in PSL. As a result of the formal verification, we found several critical logic bugs in a short time with limited resources, and successfully verified all of them. This paper presents a study of the functional verification methodology.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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