多级集相联指令高速缓存的WCET分析
WCET analysis of multi-level set-associative instruction caches
摘要：
随着实时嵌入式系统中越来越复杂的硬件的出现（具有性能增强功能的处理器，例如流水线，高速缓存层次结构，多核），许多处理器现在都有一个集关联L2高速缓存。因此，在验证实时系统的时间行为时，特别是在估计任务的最坏情况执行时间（WCET）时，需要考虑缓存层次结构。据我们所知，只有一种方法用于具有缓存层次结构的系统的WCET估计[Mueller，1997]，这对于组关联缓存来说是不安全的。在本文中，我们强调了[Mueller，1997]中描述的方法不安全的条件。提出了一种安全的静态指令缓存分析方法。与[Mueller，1997]相反，我们的方法支持集关联和全关联缓存。所提出的方法进行了实验上的中型和大型程序。我们表明，该方法是大部分的时间紧。我们进一步表明，在所有情况下，WCET的估计是更紧密的缓存层次结构时，比只考虑L1缓存。的分析时间进行评估，表明分析的缓存层次结构有一个合理的计算时间。
英文摘要：
With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, cache hierarchy, multiple cores), many processors now have a set-associative L2 cache. Thus, there is a need for considering cache hierarchies when validating the temporal behavior of real-time systems, in particular when estimating tasks' worst-case execution times (WCETs). To the best of our knowledge, there is only one approach for WCET estimation for systems with cache hierarchies [Mueller, 1997], which turns out to be unsafe for set-associative caches. In this paper, we highlight the conditions under which the approach described in [Mueller, 1997] is unsafe. A safe static instruction cache analysis method is then presented. Contrary to [Mueller, 1997] our method supports set-associative and fully associative caches. The proposed method is experimented on medium-size and large programs. We show that the method is most of the time tight. We further show that in all cases WCET estimations are much tighter when considering the cache hierarchy than when considering only the L1 cache. An evaluation of the analysis time is conducted, demonstrating that analysing the cache hierarchy has a reasonable computation time.
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