在商用同步FPGA上高效实现GALS系统：一种新方法
Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach
摘要：
提出的新的愿景是为了克服逻辑开销的问题，以前的作品展示时，应用GALS技术的可编程逻辑器件。所提出的新视图依赖于用于数据传输和时钟生成任务的基于2阶段捆绑数据奇偶校验的协议。所引入的用于智能实时延迟选择的方法的能力允许实现用于电磁干扰缓解和设备环境变化适应的各种新方法。
英文摘要：
The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol for data transfer and clock generation tasks. The ability of the introduced methodology for smart real-time delay selection allows the implementation of a variety of new methodologies for electromagnetic interference mitigation and device environment changes adaptation.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
