存储层次结构对时间受限嵌入式软件可预测性的影响
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
摘要：
安全关键的嵌入式系统必须满足实时性的限制，预计是高度可预测的，以保证在设计时，一定的时间期限将始终得到满足。这种要求通常会阻止设计人员利用高速缓存，因为它们是高度动态的，因此很难预测行为。暂存存储器的集成代表了一种替代方法，该方法允许系统受益于与高速缓存相当的性能增益，同时保持可预测性。在这项工作中，我们比较了暂存器内存和高速缓存的最坏情况下的执行时间（WCET）的分析结果的影响。我们表明，高速缓存，尽管需要复杂的技术，可以有一个负面影响的预测WCET，而估计WCET的暂存存储器规模与实现的性能增益在没有额外的分析成本。
英文摘要：
Safety-critical embedded systems having to meet real-time constraints are expected to be highly predictable in order to guarantee at design time that certain timing deadlines will always be met. This requirement usually prevents designers from utilizing caches due to their highly dynamic, thus hardly predictable behavior. The integration of scratchpad memories represents an alternative approach which allows the system to benefit from a performance gain comparable to that of caches while at the same time maintaining predictability. In this work, we compare the impact of scratchpad memories and caches on worst case execution time (WCET) analysis results. We show that caches, despite requiring complex techniques, can have a negative impact on the predicted WCET, while the estimated WCET for scratchpad memories scales with the achieved Performance gain at no extra analysis cost.
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