使用Fast DAC和FPGA的快速灵活的PDKEEPAAA驱动系统
Fast and Flexible CCD Driver System Using Fast DAC and FPGA
摘要：
我们开发了一种全新的通用CCD数据采集系统，它使人们能够使用任何类型的时钟模式驱动任何类型的CCD。以前广泛使用的CCD驱动器系统由模拟多路复用器（MPX）、数模转换器（DAC）和运算放大器组成。DAC用于确定高和低电压电平，MPX使用TTL时钟选择每个电压电平。在这种驱动电路中，由于MPX的高电平和低电平之间的短路而产生的噪声难以降低，并且需要选择多种不同的电压电平。半导体集成电路的最新发展使我们能够使用一个非常快速的采样（$\sim$ 10 MHz）DAC，成本低。因此，我们开发了新的驱动器系统，使用快速DAC，以确定时钟的电压电平和时钟定时。采用FPGA（Field Programmable Gate Array）实现对DAC的控制。我们已经建立了数据采集系统，并发现CCD功能良好，我们的新系统。Mn K $α$的能量分辨率为$\simeq$ 150 eV，读出噪声为$\simeq$ 8 e $^-$ .
英文摘要：
We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer (MPX), a digital-to-analog converter (DAC), and an operational amplifier. A DAC is used to determine high and low voltage levels and the MPX selects each voltage level using a TTL clock. In this kind of driver board, it is difficult to reduce the noise caused by a short of high and low level in MPX and also to select many kinds of different voltage levels. Recent developments in semiconductor IC enable us to use a very fast sampling ($\sim$ 10MHz) DAC with low cost. We thus develop the new driver system using a fast DAC in order to determine both the voltage level of the clock and the clocking timing. We use FPGA (Field Programmable Gate Array) to control the DAC. We have constructed the data acquisition system and found that the CCD functions well with our new system. The energy resolution of Mn K$α$ has a full-width at half-maximum of $\simeq$ 150 eV and the readout noise of our system is $\simeq$ 8 e$^-$.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
