基于印刷忆阻器的低延迟有状态逻辑加法器的跨层协同设计
Cross-Layer Co-Design of Low-Latency Stateful Logic Adders with Printed Memristors
AI总结：
本研究针对数据中心系统的数据传输瓶颈，将器件、逻辑、架构层协同设计，提出基于印刷ECM忆阻器的混合MAGIC与FELIX逻辑的有状态加法器，实现了3.7-16.4倍的工作负载加速。
摘要：
数据中心系统中，存储单元与处理单元之间的数据传输仍是主要瓶颈。忆阻有状态逻辑（SL）通过直接对存储的阻性状态执行布尔运算来解决该问题。然而，算术效率取决于器件支持的逻辑原语集、所得运算序列的依赖结构及其到数据通路架构的映射。现有设计通常分别优化器件、逻辑和架构层，而本研究将三者结合，协同设计一种有状态加法器。实验在印刷电化学金属化（ECM）忆阻器上演示了混合MAGIC与FELIX逻辑原语集，并推导了针对位间进位传播优化的全加器序列。将该序列映射到位串行、位并行和位流水线数据通路，后两者的n位加法仅需2n+6个周期；对于32位加法，其周期数较现有SL加法器减少60%-88%。在四个代表性工作负载上，本研究实现了较现有方案3.7倍至16.4倍的加速比。这些结果表明跨层协同设计可转化为工作负载级性能提升。
英文摘要：
Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean operations directly on stored resistive states. However, arithmetic efficiency depends jointly on the device-supported logic primitive set, the dependency structure of the resulting operation sequence, and its mapping to datapath architectures. While prior designs typically optimize device, logic, and architecture layers separately, we jointly consider them to co-design a stateful adder. We experimentally demonstrate a mixed MAGIC and FELIX logic primitive set on printed Electrochemical Metallization (ECM) memristors and derive a full adder sequence optimized for inter-bit carry propagation. Mapping this sequence to bit-serial, bit-parallel, and bit-pipelined datapaths reduces the latter two to 2n+6 cycles for an n-bit addition. For 32-bit addition, this requires 60-88% fewer cycles than prior SL adders. Across four representative workloads, we achieve 3.7x-16.4x speedup over prior. These results show how cross-layer co-design can translate into improved workload-level performance.
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