发表机构
InfiniTree; Kyung Hee University（InfiniTree; 庆熙大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出ATLAS，一种结合拓扑数据分析（TDA）的贝叶斯优化框架，用于解决模拟晶体管尺寸优化中现有方法的拓扑盲性问题，实验显示其仅需更少仿真次数即可找到可行设计，是首个将TDA应用于模拟电路设计自动化的工作。
AI 中文摘要
模拟晶体管尺寸优化是寻找同时满足多个性能指标的设计参数，是电路设计中劳动密集型的瓶颈环节。为辅助模拟电路专家，已提出多种自动化方法，包括贝叶斯优化（BO）、强化学习（RL）等。然而现有方法未考虑可行设计空间的拓扑结构，该空间会因工作区域转换、指标权衡冲突及非凸器件物理特性分裂为不连通区域，这种拓扑盲性会导致优化器收敛于单个可行区域，错过可能包含更优设计的其他区域。为解决该局限，本文提出ATLAS，一种利用拓扑数据分析（TDA）的贝叶斯优化框架。在每次迭代中，会在代理模型预测的可行区域上构建Mapper图以估计连通区域，无需任何观测到的可行点即可从首次迭代开始实现感知拓扑的探索。拓扑敏感度分数将候选点分类为桥点、边界点或内部点，为采集函数注入针对性的探索奖励。在GF180和SKY130工艺的四个模拟电路基准测试上的实验表明，ATLAS相较于包括RL和BO在内的基线方法，仅需显著更少的仿真次数即可找到可行设计。据我们所知，这是首个将拓扑数据分析应用于模拟电路设计自动化的工作，其官方实现可在该httpsURL获取。
英文摘要
Analog transistor sizing, finding design parameters that simultaneously satisfy multiple performance specifications, is a labor-intensive bottleneck in circuit design. To support analog circuit experts, various automation methods have been proposed, including Bayesian optimization (BO), reinforcement learning (RL), and others. Yet existing methods are oblivious to the topological structure of a feasible design space, which can fragment into disconnected regions due to operating-regime transitions, conflicting specification trade-offs, and nonconvex device physics. This topological blindness causes the optimizer to converge within a single feasible region while missing others that may contain superior designs. To address this limitation, we propose ATLAS. a BO framework utilizing Topological Data Analysis (TDA). At each iteration, a Mapper graph is constructed over a surrogate-predicted feasible region to estimate connected regions, enabling topology-aware exploration from the very first iteration without any observed feasible points. A topological sensitivity score classifies candidates as bridge, frontier, or interior points, injecting a targeted exploration bonus into the acquisition function. Experiments on four analog circuit benchmarks in the GF180 and SKY130 processes demonstrate that \coin finds feasible designs with significantly fewer simulations than baselines, including RL and BO methods. To the best of our knowledge, this is the first work to apply topological data analysis to analog circuit design automation. The official implementation is publicly available on https://github.com/youngmin0oh/atlas.
