发表机构
Stanford University; University of California, Davis; Univ. Grenoble Alpes; CEA, Leti; Université Catholique de Louvain（斯坦福大学; 加州大学戴维斯分校; 格勒诺布尔阿尔卑斯大学; 法国原子能和替代能源委员会柳特研究院; 天主教鲁汶大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
该研究针对二维半导体的带尾态问题，建立物理电学模型，提出缓解带尾态影响的方法，为其在低功耗纳米电子学中的应用提供理论框架与设计指南。
AI 中文摘要
我们提出，要充分发挥二维（2D）电子学的潜力，关键在于理解并掌握其能带尾态（BTS）。与受益于陡峭带边（Urbach能量$E_\rm U$约10meV）的硅不同，当前的单层二维半导体因空间势不均匀性，带边粗糙（$E_\rm U$约100meV）。通过将基于物理的电学模型与实验对比，我们证明BTS会导致单层二维晶体管的有效迁移率降低，且在栅极电压过高时出现“缓慢”的晶体管开启，这为其节能运行设置了基本限制。我们还表明，只要将$E_\rm U$降至约50meV以下，可通过提高栅极电容、应变工程，以及使用双层而非单层二维沟道来缓解二维晶体管中的BTS效应。本研究提供了一个理论框架和设计指南，以应对这些基本限制，并推动二维半导体成功集成到低功耗纳米电子学中。
英文摘要
We propose that the path to realizing the full potential of two-dimensional (2D) electronics lies in understanding and mastering their energy band tail states (BTS). Unlike silicon, which benefits from sharp band edges (Urbach energy $E_\rm U$ ~ 10 meV), today's monolayer 2D semiconductors have rough band edges ($E_\rm U$ ~ 100 meV) caused by spatial potential inhomogeneity. Comparing a physics-based electrical model to experiments, we demonstrate that BTS cause reduced effective mobility and "slow" transistor turn-on with excessive gate voltage in monolayer 2D transistors, which sets a fundamental limit for their energy-efficient operation. We also show that BTS effects in 2D transistors could be mitigated with higher gate capacitance, with strain engineering, and by using bilayer instead of monolayer 2D channels, as long as $E_\rm U$ is reduced below ~ 50 meV. This work provides a theoretical framework and design guidelines to navigate these fundamental limits, and to enable successful integration of 2D semiconductors into low-power nanoelectronics.
