发表机构
Central South University（中南大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
针对H.266/VVC依赖量化实时性差的问题，提出一种低BDBR损失的交叉并行硬件架构，通过时分复用实现四通道并行，在FPGA和ASIC上显著提升量化速度。
AI 中文摘要
虽然H.266/VVC中的依赖量化实现了高压缩比，但其强串行特性和高复杂度导致实时性能较差，难以在实际场景中部署。为了在最小化压缩性能损失的前提下提升依赖量化的实时性能，我们提出了一种具有低BDBR损失的交叉并行依赖量化硬件架构，通过时分复用大部分组合逻辑实现四通道并行依赖量化。该架构采用了所提出的CG内上下文简化方案以及在码率估计期间跳过decAbslevel的编码方案。所提出的设计在All Intra配置下仅产生0.42%的BDBR损失，在Random Access配置下为0.38%。该依赖量化硬件架构使用Verilog HDL实现，在Xilinx XCZU19 FPGA上实现时，在QP=22、27、32和37下分别达到4K@33.2、91.4、331.2和454.1 fps的量化速度。当使用TSMC 28nm工艺标准单元库在ASIC上实现时，相应的量化速度分别达到4K@84.0、231.0、837.0和1147.7 fps。
英文摘要
While dependent quantization in H.266/VVC delivers a high compression ratio, its strong serial nature and high complexity result in poor real-time performance, making it difficult to deploy in practical scenarios. To improve the real-time performance of dependent quantization with minimal degradation to its compression performance, we propose a interleaved parallel dependent quantization hardware architecture with low BDBR loss, which achieves four-channel parallel dependent quantization by time-division multiplexing most combinational logic. This architecture adopts the proposed intra-CG context simplification scheme and the encoding scheme that skips decAbslevel during rate estimation. The proposed design incurs a BDBR loss of only 0.42% under the All Intra configuration and 0.38% under the Random Access configuration, respectively. Implemented in Verilog HDL, the dependent quantization hardware architecture achieves quantization speeds of 4K@33.2, 91.4, 331.2, and 454.1 fps at QP = 22, 27, 32, and 37, respectively, when implemented on the Xilinx XCZU19 FPGA. When implemented on ASIC using the TSMC 28nm process standard cell library, the corresponding quantization speeds reach 4K@84.0, 231.0, 837.0, and 1147.7 fps.
