发表机构
ETH Zürich; New York University（苏黎世联邦理工学院; 纽约大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
Trail是一种时间性TLB预取器，利用页表项未用位存储增量，随内存足迹扩展，无需额外存储，平均提升单核性能5.7%，四核11.5%。
AI 中文摘要
地址翻译是数据密集型工作负载中的主要瓶颈。TLB预取可以隐藏翻译延迟，但现有的空间预取器难以应对不规则访问，而时间性预取器将地址增量存储在固定容量的硬件中，无法随应用程序内存足迹扩展。我们对200个翻译密集型工作负载的特征分析表明，每个虚拟内存区域都有一小组重复出现的增量，且超过94%的增量适合用18位有符号数表示。我们提出了Trail，一种时间性TLB预取器，将增量存储在叶页表项（PTE）的未使用位中。当某个区域触发页表遍历时，Trail识别出上次从同一指令触发遍历的区域，并将它们的增量记录在该源区域的PTE中。当后续遍历获取源区域的PTE缓存块时，Trail无需额外内存访问即可检索其增量，并将可能目标区域的翻译预取到TLB和缓存层次结构中。每个PTE缓存块存储多个增量可提高覆盖率，而使用现有PTE位使得元数据容量能够随应用程序的内存足迹扩展，无需额外元数据存储。在200个工作负载和100个多程序混合负载中，与无TLB预取的基线相比，Trail平均将单核（四核）性能提升了5.7%（11.5%），比先前最佳的独立TLB预取器高出1.7%（2.5%）。Trail仅需一个64项硬件表来跟踪每条指令的页表遍历历史。Trail可从此https URL免费获取。
英文摘要
Address translation is a major bottleneck in data-intensive workloads. TLB prefetching can hide translation latency, but existing spatial prefetchers struggle with irregular accesses, while temporal prefetchers store address deltas in fixed-capacity hardware that cannot scale with application memory footprints. Our characterization of 200 translation-intensive workloads reveals that each virtual memory region has a small, recurring set of deltas, and over 94% of deltas fit in 18 signed bits. We introduce Trail, a temporal TLB prefetcher that stores deltas in unused bits of leaf page table entries (PTEs). When a region triggers a page table walk, Trail identifies the region that last triggered a walk from the same instruction and records their delta in that source region's PTE. When a later walk fetches the source region's PTE cache block, Trail retrieves its deltas without additional memory accesses and prefetches translations for likely destination regions into the TLBs and cache hierarchy. Storing multiple deltas per PTE cache block improves coverage, while using existing PTE bits allows metadata capacity to scale with the application's memory footprint without additional metadata storage. Across 200 workloads and 100 multiprogrammed mixes, Trail improves single-core (four-core) performance by 5.7% (11.5%) on average over a baseline without TLB prefetching, outperforming the best prior standalone TLB prefetcher by 1.7% (2.5%). Trail requires only a 64-entry hardware table to track per-instruction page table walk history. Trail is freely available at https://github.com/CMU-SAFARI/Virtuoso/tree/trail-artifact-release.
