发表机构
Seoul National University（首尔大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
vTen通过声明式DSL和内核级批处理解耦验证意图与执行，减少主机-模拟器交互，在3D U-Net加速器上实现2倍模拟加速和60.3%代码简化。
AI 中文摘要
张量中心软件模型与信号级硬件测试平台之间的语义鸿沟在验证领域专用加速器（DSA）时造成了显著的生产力瓶颈。现有框架如Cocotb因细粒度交互而遭受过高的同步开销。为解决此问题，我们提出vTen，一个数据中心的框架，严格将验证意图与执行机制解耦。通过利用声明式DSL和内核级批处理，vTen最小化主机与模拟器之间的交互频率。在生产规模的3D U-Net加速器上的评估表明，与Cocotb相比，vTen在模拟延迟上实现了2倍的性能提升，并将代码复杂度降低了60.3%。
英文摘要
The semantic gap between tensor-centric software models and signal-level hardware testbenches creates significant productivity bottlenecks in verifying Domain-Specific Accelerators (DSAs). Existing frameworks like Cocotb suffer from prohibitive synchronization overheads due to fine-grained interactions. To address this, we propose vTen, a data-centric framework that strictly decouples verification intent from execution mechanics. By leveraging a declarative DSL and kernel-granular batching, vTen minimizes host-simulator interaction frequency. Evaluation on a production-scale 3D U-Net accelerator demonstrates that vTen achieves a 2x performance improvement in simulation latency and a 60.3% reduction in code complexity compared to Cocotb.
Comments7 pages, 8 figures, 1 table. Accepted at the 63rd ACM/IEEE Design Automation Conference (DAC '26), Long Beach, CA, USA
