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基于FPGA的μ子簇射识别与图神经网络跟踪算法用于HL-LHC触发器

FPGA-based muon shower identification and graph neural network tracking algorithms for HL-LHC triggers

Daniel Estrada, Elena Aller, Andrea Cardini, Santiago Folgueras, Pelayo Leguina, Javier Prado

arXiv 2610.06379首次发表:更新:

AI 中文总结

针对HL-LHC触发器,提出FPGA上的μ子簇射识别与图神经网络跟踪算法,分别处理桶部与重叠区域,通过INT8-PO2量化和位宽优化,将DSP利用率降至20%,推理延迟仅19个时钟周期,为长寿命粒子等非常规μ子特征触发奠定基础。

AI 中文摘要

这项工作提出了两种硬件加速策略,用于CMS一级触发器(L1T)的升级,以应对高能辐射μ子及非常规物理特征(如长寿命粒子(LLPs))导致的效率损失。第一种策略直接处理低层级探测器击中信息,在CMS桶部区域实现了一种专用的μ子簇射识别算法,该算法监测漂移管室中的击中多重性以生成簇射原语。该算法以亚束团交叉延迟和超低资源消耗运行,成功标记了簇射μ子,并为下游径迹查找器提供了必要的上下文。第二种策略针对桶部-端盖过渡(重叠)区域,通过评估图神经网络来重建偏移的μ子径迹。采用一种先隔离硬件可行性、再考虑物理改进的分步方法,首先评估了基于GraphSAGE架构的初始代理模型,以验证其在严格延迟限制下在FPGA上的可行性。该实现采用了INT8-PO2量化技术,并结合了数据驱动的位宽优化。通过用快速的编译时算术位移替代依赖DSP的定点乘法,并为每个信号分配所需的最小位数,这种硬件-软件协同设计将DSP利用率降低至20%,并实现了仅19个时钟周期的确定性推理延迟。这些进展共同为在一级触发器上触发非标准μ子特征(如来自LLP衰变的特征)铺平了道路。

英文摘要

This work presents two hardware-accelerated strategies for the upgrade of the CMS Level-1 Trigger (L1T) to target efficiency losses due to highly energetic radiating muons and unconventional physics signatures, such as Long-Lived Particles (LLPs). Operating directly on low-level detector hits, the first strategy implements a dedicated muon shower identification algorithm in the CMS barrel region that monitors hit multiplicities in the Drift Tube chambers to generate Shower Primitives. Executing with sub-bunch-crossing latency and ultra-low resource consumption, this algorithm successfully tags showered muons and provides essential context for downstream track finders. The second approach targets the barrel-endcap transition (overlap) region by evaluating Graph Neural Networks to reconstruct displaced muon tracks. Following a divided methodology that first isolates hardware feasibility from evolving physics refinements, an initial proxy model based on a GraphSAGE architecture is evaluated to validate its viability on FPGAs within strict latency limits. This implementation utilizes an INT8-PO2 quantization technique coupled with a data-driven bit-width optimization. By replacing DSP-heavy fixed-point multiplications with fast compile-time arithmetic bit-shifts and allocating the minimum required bits per signal, this hardware-software co-design reduces DSP utilization to $20\%$ and achieves a deterministic inference latency of just $19$ clock cycles. Together, these developments pave the way for triggering on non-standard muon signatures, such as those from LLP decays, at L1T.

CommentsWork originally presented at the 27th International Workshop on Radiation Imaging Detectors (iWoRID 2026)

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