发表机构
University of Oulu; Wuhan University（奥卢大学; 武汉大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本研究探讨量子编译中表示变化导致综合可用性丧失的问题，提出Verified方法记录并验证高级操作以恢复综合，实验证明其有效恢复请求的综合。
AI 中文摘要
量子编译器将高级操作（如量子傅里叶变换和多控X门）合成为门级电路。在编译的各阶段中，电路可能被序列化、以OpenQASM格式交换、在不同编译器之间转换，或被降级为门操作。这些表示形式的改变可以在保留计算的同时移除高级操作本身，使得接收编译器无法应用所请求的综合方法。我们将此称为综合可用性丧失。我们通过受控实验、仓库分析、从项目测试中捕获的电路以及慕尼黑量子工具包流水线，在Qiskit、TKET和Cirq中研究了综合可用性。当反序列化恢复高级操作时，综合可用性在序列化后得以保留；仅当接收编译器支持该操作时，综合可用性才能在编译器转换后得以保留。它无法在所评估的OpenQASM路线中幸存。在直接的OpenQASM 3往返之后，在所有360个交付条件下，所请求的综合没有效果，尽管编译成功。在MQT流水线中，OpenQASM 2交换使八量子比特Grover电路的双量子比特门数量增加了37.2%。我们还引入了Verified，它在表示变化之前记录高级操作，并且仅当检查确认记录仍然与交付的电路匹配时才重建它们。Verified在所有830次恢复运行中恢复了所请求的综合，每个操作族的中位验证时间从2.0毫秒到638毫秒不等。该检查拒绝了所有过时记录，但也拒绝了一些有效记录。这些结果表明，当后续综合选择依赖于保留的高级结构时，仅保持功能等价是不够的。
英文摘要
Quantum compilers synthesize high-level operations, such as the quantum Fourier transform and multi-controlled X gates, into gate-level circuits. Across compilation stages, a circuit may be serialized, exchanged as OpenQASM, converted between compilers, or lowered to gates. These representation changes can preserve computation while removing the high-level operation itself, leaving the receiving compiler unable to apply a requested synthesis method. We call this loss synthesis availability. We study synthesis availability in Qiskit, TKET, and Cirq through controlled experiments, repository analysis, circuits captured from project tests, and a Munich Quantum Toolkit pipeline. Synthesis availability survives serialization when deserialization restores the high-level operation and survives compiler conversion only when the receiving compiler supports that operation. It does not survive the evaluated OpenQASM routes. After a direct OpenQASM 3 round trip, requested synthesis has no effect in all 360 delivered conditions even though compilation succeeds. In the MQT pipeline, OpenQASM 2 interchange increases the two-qubit gate count by 37.2 percent for an eight-qubit Grover circuit. We also introduce Verified, which records high-level operations before a representation change and reconstructs them only when a check confirms that the record still matches the delivered circuit. Verified restores requested synthesis in all 830 recovery runs, with median verification times from 2.0 to 638 ms per operation family. The check rejects every stale record but also some valid records. These results show that preserving functional equivalence alone is insufficient when later synthesis choices depend on retained high-level structure.
Comments21 pages
