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一种采用28纳米CMOS工艺、通过编程多级状态进行偏移校准的FeFET电压-时间转换器

A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS

Jeries Mattar, Hanaa Eqeiq, Stefan Dünkel, Halid Mulaosmanovic, Gunda Beernink, Sven Beyer, Nicolás Wainstein

arXiv 2610.05016首次发表:更新:

发表机构

Andrew and Erna Viterbi Faculty of Electrical and Computer Engineering, Technion - Israel Institute of Technology; Astera Labs, Israel; GlobalFoundries Fab1 LLC and Co. KG, Dresden, Germany(安德鲁和埃尔纳·维特比电气与计算机工程学院,以色列理工学院; Astera Labs,以色列; GlobalFoundries Fab1有限责任公司及合伙公司,德国德累斯顿)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

本文提出一种基于FeFET多级编程状态的VTC,通过非易失性偏移校准改善性能,在28nm CMOS工艺下实现,显著降低谐波失真和INL,并支持高速低功耗运行。

AI 中文摘要

时域电路中的电压-时间转换器(VTC)的偏移和增益会随工艺、电源和温度的变化而变化。本工作提出了一种VTC,其非易失性输入参考偏移校准是通过转换输入的铁电场效应晶体管(FeFET)的编程多级状态来实现的。该VTC采用28纳米CMOS工艺制造,面积为6.07平方微米,由一个电流饥饿型反相器(其尾部包含FeFET和一个并联的NMOS泄漏晶体管)、一个电容阵列以及一个后续反相器组成。编程状态将传输曲线移动到输入范围内,而增益则留给电容阵列和泄漏晶体管的偏置。在10兆样本/秒的测量下,中心化状态将二次谐波从低阈值状态下的-12.5分贝减弱至-32.2分贝,并将5位时的静态积分非线性(INL)从2.42 LSB降低至0.92 LSB。布局后仿真表明,所提出的VTC可以在500兆样本/秒下工作,从0.9伏电源汲取2.0微瓦功率,并且在高达700兆样本/秒时失真和增益几乎不变。在仿真的工艺角以及±10%的电源电压变化下,通过调整编程状态和泄漏晶体管偏置,输入参考偏移被校准到10毫伏以内,增益被校准到标称值的4%以内。

英文摘要

The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referred offset trim is the programmed multilevel state of the ferroelectric field-effect transistor (FeFET) that converts the input. Fabricated in 28-nm CMOS, the 6.07-$μ$m$^2$ VTC consists of a current-starved inverter with the FeFET and a parallel NMOS leaker in its tail, a capacitor bank, and a following inverter. The programmed state shifts the transfer curve onto the input range, leaving the gain to the capacitor bank and the leaker bias. Measured at 10~MS/s, centered states weaken the second harmonic from $-$12.5~dB in the low-threshold state to $-$32.2~dB and lower the static integral nonlinearity (INL) at 5~bit from 2.42 to 0.92~LSB. Post-layout simulations indicate that the proposed VTC can operate at 500~MS/s, drawing 2.0~$μ$W from a 0.9-V supply, with nearly unchanged distortion and gain up to 700~MS/s. Across simulated process corners and $\pm$10\,\% supply variation, the input-referred offset is calibrated to within 10~mV and the gain to within 4\,\% of nominal by adjusting the programmed state and leaker bias.

论文原文

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