发表机构
Faculty of Engineering and Natural Sciences, Sabancı University; Graduate School of Advanced Science and Engineering, Hiroshima University（萨班哲大学工程与自然科学学院; 广岛大学先进理工学研究科）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出一种基于TSMC 65 nm CMOS的分布式倍频器，利用四分之一波长传输线终端增强输出功率，在188-260 GHz范围内实现4 dBm饱和输出，适用于亚太赫兹低相位噪声信号源。
AI 中文摘要
亚太赫兹（sub-THz）低相位噪声信号源通常采用倍频器链来扩展较低频率振荡器的工作频率。本文介绍了采用TSMC 65 nm CMOS工艺实现的宽带、高输出功率倍频器的设计与仿真。所提出的设计基于一种分布式倍频器，在漏极侧采用四分之一波长传输线终端，使反射波与正向传播波相长合并以增强输出功率。该倍频器在输入频率为115 GHz、输入功率为12 dBm时，实现了12 dB的最小转换损耗，输出功率为0 dBm，基波抑制为12.6 dB。在相同输入功率下，输出功率在188-260 GHz输出频率范围内保持在峰值3 dB以内。在230 GHz时，该设计实现了4 dBm的饱和输出功率，占用面积为0.149 mm²。
英文摘要
Sub-terahertz (sub-THz) low-phase-noise signal sources commonly employ frequency multiplier chains to extend the operating frequency of lower-frequency oscillators. This paper presents the design and simulations of a wideband, high-output-power frequency multiplier implemented in TSMC 65 nm CMOS technology. The proposed design is based on a distributed frequency multiplier with a quarter-wave transmission line termination at the drain side, where the reflected and forward-traveling waves are constructively combined to enhance the output power. The proposed frequency doubler achieves a minimum conversion loss of 12 dB at an input frequency of 115 GHz with an input power of 12 dBm, resulting in an output power of 0 dBm and 12.6 dB fundamental suppression. For the same input power, the output power remains within 3 dB of its peak value over the 188-260 GHz output frequency range. At 230 GHz, the proposed design achieves a saturated output power of 4 dBm while occupying an area of 0.149 mm^2.
CommentsLatin America Microwave Conferance 2026
