通过错误归因优化量子纠错

中文摘要 AI 辅助

逻辑错误率是量子纠错的标准基准，提供了物理噪声整体效应的聚合度量。在实际的QEC架构中，即使不同电路位置上的错误概率相等，它们对逻辑故障的影响也可能显著不同。这里我们引入一种错误归因方案，以定量表征各个电路组件对逻辑错误率的影响，并利用这一精细化信息指导有针对性的干预和设计，以提升QEC性能。我们的归因估计器从用于估计逻辑错误率的同一组蒙特卡洛样本中联合计算所有组件的灵敏度。由此产生的灵敏度图识别出热点区域，在这些区域中，有针对性的噪声降低能最有效地改善逻辑性能。我们在旋转表面码存储器和高速率提升乘积码的电路模拟中测试了该方案：在按灵敏度选择的约5%-7%的物理组件上将噪声强度减半，可将逻辑错误率降低约15%-25%，大约是同等数量随机选择组件上相同干预所带来平均降低幅度的两倍。通过将性能基准测试与有针对性的优化联系起来，我们的方案为在有限资源下改进量子纠错提供了一种实用策略。

英文摘要

Logical error rate is a standard benchmark for quantum error correction, providing an aggregate measure of the overall effect of physical noise. In actual QEC architectures, errors at different circuit locations can have markedly different effects on logical failure even when their probabilities are equal. Here we introduce an error attribution scheme to quantitatively characterize the influence of individual circuit components on the logical error rate and use this refined information to guide targeted intervention and design for improved QEC performance. Our attribution estimator computes all component sensitivities jointly from the same Monte Carlo samples used to estimate the logical error rate. The resulting sensitivity maps identify hotspots where targeted noise reduction can most effectively improve logical performance. We test the scheme in circuit simulations of rotated surface code memories and high-rate lifted product codes: halving the noise strength on about 5\%-7\% of physical components selected by sensitivity reduces logical error rates by approximately 15\%-25\%, roughly twice the mean reduction from the same intervention on an equal number of randomly selected components. By connecting performance benchmarking to targeted optimization, our scheme provides a practical strategy for improving quantum error correction with limited resources.

发表机构

• Yau Mathematical Sciences Center, Tsinghua University（丘成桐数学科学中心，清华大学）
• Yanqi Lake Beijing Institute of Mathematical Sciences and Applications（燕京数学科学与应用研究院）

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