发表机构
The University of Tokyo; RIKEN（东京大学; 理化学研究所）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文提出一种基于MLIR的编译器，利用声明式注释将CUDA HPC内核迁移至Tenstorrent Blackhole，实现空间映射与核间协调，在多个基准上获得最高4.2倍加速。
AI 中文摘要
Tenstorrent Blackhole结合了分布式本地存储器、显式核间通信以及将数据移动与计算解耦的Tensix核。CUDA提供了庞大的高性能计算（HPC）软件基础，但物理数据放置和调度在很大程度上是隐式的。将CUDA HPC内核迁移到Blackhole需要跨核的空间映射以及每个核上计算和数据移动内核的协调。我们提出了一种基于MLIR的编译器，从静态形状的仿射CUDA子集推导数据放置、核间通信和瓦片计算。声明式注释表达了源中未固定的选择，包括计算/数据移动操作放置和流式传输粒度。我们在高斯消元、五点模板和对称秩k更新上对其进行了评估。相对于我们编译器的默认实现，最佳测量配置在BF16高斯消元上实现了4.2倍加速，在FP32高斯消元和雅可比迭代上实现了2.1-2.2倍加速。一个选择的性能影响可能随着周围策略、精度和循环调度而逆转，这促使比较替代的每核实现而非独立策略选择。
英文摘要
Tenstorrent Blackhole combines distributed local memories, explicit inter-core communication, and Tensix cores decoupling data movement from computation. CUDA offers a substantial HPC software base but leaves physical data placement and scheduling largely implicit. Migrating CUDA HPC kernels to Blackhole requires spatial mapping across cores and per-core coordination of compute and data-movement kernels. We present an MLIR-based compiler deriving data placement, inter-core communication, and tile computation from a statically shaped affine CUDA subset. Declarative annotations express choices not fixed by the source, including compute/DM operation placement and streaming granularity. We evaluate it on Gaussian elimination, five-point stencil, and symmetric rank-k update. Relative to our compiler's default realizations, the best measured configurations achieve a 4.2x speedup for BF16 Gaussian and 2.1-2.2x for FP32 Gaussian and Jacobi. A choice's performance impact can reverse with surrounding policies, precision, and loop schedule, motivating comparison of alternative per-core realizations rather than independent policy selection.
CommentsAccepted at the Thirteenth Workshop on Accelerator Programming and Directives (WACCPD 2026)
