发表机构
UC Santa Cruz（加州大学圣克鲁兹分校）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
该研究首次探索2纳米GAAFET BSPDN技术中的背面时钟网格设计空间，通过多目标贝叶斯优化和SPICE验证，证明其相比正面网格平均降低45%偏斜、25%转换时间、4.5%功耗及28%布线。
AI 中文摘要
时钟网格在高性能VLSI设计中用于最小化时钟偏斜并容忍片上变化，但它们在优质金属层上消耗了稀缺的布线资源。背面供电网络提供了一种新选择：它在晶圆背面增加了厚且低电阻的金属层，而供电网络并未占用所有这些金属层。触发器仍位于正面；因此，背面网格无法直接驱动它们，每个连接都必须通过硅通孔。我们首次对背面时钟网格进行了设计空间探索，并在基于2纳米纳米片技术的GT2N上通过OpenROAD实现。我们使用多目标贝叶斯优化探索了四个基准设计（包含1,938至15,311个触发器），并且由于循环网格无法通过静态时序分析进行评估，每个设计点都通过晶体管级SPICE仿真进行了验证。在所有四个设计中，背面网格始终优于相同的正面网格，平均偏斜降低45%，汇点转换时间降低25%，功耗降低4.5%，正面时钟布线减少28%，并且在10,000样本蒙特卡洛模拟下的偏斜分布仅为正面网格的三分之一。
英文摘要
Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.
