面向超导电路最小化的重复感知重定时与单元接口重设计
Duplication-Aware Retiming and Cell Interface Redesign for Superconductor Circuit Minimization
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中文总结 AI 辅助
针对超导电路因双轨编码导致的门重复问题，提出重复感知重定时方法协同优化寄存器与极性，并设计新放大器降低单元接口开销，实现JJ数量显著减少并建立新的帕累托前沿。
中文摘要 AI 辅助
超导电子学已日益从RSFQ及其变体转向消除显式门级时钟的逻辑族。虽然这一转变使得电路更简单、架构更高效，但也引入了对双轨编码的隐式依赖，导致固有的门重复。本工作提出了一种面向约瑟夫森结（JJ）数量最小化的重复感知重定时方法，协同优化寄存器放置和极性分配。该方法适用于SFQ之外的任何单调电路。我们进一步识别出单元接口——特别是互连驱动器、接收器和扇出（FO）元件——是每个单元中JJ数量的主要贡献者。引入了一种新的放大器设计以降低这些成本，集成在现有SFQ单元中，经过实验验证并表征，形成了新的SFQ单元库。我们的结果表明，与先前最先进技术相比，单周期实现中JJ数量减少63-71%，多周期实现中减少41-66%。后者建立了新的帕累托前沿，实现了比迄今最佳单周期实现更短的关键路径和更低的JJ数量。
英文摘要
Superconductor electronics have increasingly shifted away from RSFQ and its variants toward logic families that eliminate explicit gate-level clocking. While this transition enables simpler circuits and more efficient architectures, it also introduces an implicit reliance on dual-rail codes, resulting in inherent gate duplication. This work presents a duplication-aware retiming methodology for Josephson junction (JJ) count minimization, co-optimizing register placement and polarity assignment. The approach applies beyond SFQ to any monotonic circuit. We further identify cell interfaces---specifically, interconnect drivers, receivers, and fanout (FO) elements---as dominant contributors to JJ count in each cell. A new amplifier design is introduced to reduce these costs, integrated within existing SFQ cells, experimentally verified, and characterized to form a new SFQ cell library. Our results demonstrate a 63-71% JJ count reduction in single-cycle implementations and 41-66% reduction in multi-cycle implementations compared to the prior state-of-the-art. The latter establishes a new Pareto frontier, achieving both shorter critical paths and lower JJ counts than the best-to-date single-cycle implementations.
发表机构
- University of Wisconsin - Madison（威斯康星大学麦迪逊分校）
- University of Michigan（密歇根大学）
机构由 AI 辅助整理，请以论文原文为准。
