发表机构
Ampere Computing（安培计算）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文介绍Ampere Computing开源的两件性能分析工具：事件流格式和Catscan可视化器，用于在硅片前调试CPU性能，并分享其设计经验与教训。
AI 中文摘要
处理器流水线可视化工具在工业界的CPU团队中很常见，但其中很少有被公开描述或发布的。因此，学生、研究人员和其他从业者很少能看到处理器架构师在硅片之前用于调试性能的工具。本文描述了Ampere Computing公司性能分析基础设施中的两个部分，我们已将其作为开源发布给社区：事件流（一种仿真器输出格式）和Catscan（一个围绕该格式构建的交互式查看器）。事件流将微架构活动记录为通过事务关系连接的类型化事件，因此用户可以在症状与解释该症状的指令、微操作或内存事务之间移动。Catscan利用该结构支持面向资源和事务的视图、持久高亮、领域特定搜索、比较性迹线同步以及产品开发期间使用的其他工作流程。在本文中，我们报告了在生产使用中幸存下来的设计选择、我们遇到的局限性以及我们认为对未来微架构可视化工具有用的经验教训。
英文摘要
Processor pipeline visualization tools are routine inside industry CPU teams, but few of them are described or released publicly. As a result, students, researchers, and other practitioners rarely see the tooling that processor architects use to debug performance before silicon. This paper describes two pieces of Ampere Computing's performance- analysis infrastructure that we have released to the community as open source: event streams, a simulator-output format, and Catscan, an interactive viewer built around that format. Event streams record microarchitectural activity as typed events connected by transaction relationships, so a user can move between a symptom and the instruction, uop, or memory transaction that explains it. Catscan uses that structure to support resource- and transaction-oriented views, persistent highlighting, domain-specific search, comparative trace synchronization, and other workflows used during product development. In this paper we report the design choices that survived production use, the limitations we encountered, and the lessons we think are useful for future microarchitectural visualization tools.
