arXivDaily arXiv每日学术速递 周一至周五更新
arXiv周末暂无论文更新,休息一下吧,周末愉快~~

基于局部物理上下文的时序驱动逻辑重映射

Timing-Driven Logic Remapping with Local Physical Context

Zijian Jiang, Hongyang Pan, Cunqing Lan, Keren Zhu

arXiv 2610.01918首次发表:更新:

发表机构

State Key Laboratory of ASIC and System, Fudan University(复旦大学)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

提出一个结合离散映射搜索与物理反馈的框架,通过有界窗口和混合整数公式在布局后局部重映射逻辑,以优化时序。

AI 中文摘要

映射电路(mapped circuit)的时序行为既取决于其逻辑实现,也取决于该实现所处的物理环境。因此,在布局(placement)之后重新审视映射决策,需要一种能够考虑周围时序约束、扇出负载和互连效应的搜索过程。我们在此背景下研究局部重映射(local remapping),并开发了一个将离散映射搜索与物理实现反馈相结合的框架。时序关键区域通过有界窗口(bounded windows)进行隔离,这些窗口的接口保留了周围电路的上下文。在每个窗口内,一个混合整数(mixed-integer)公式在由估计位置和互连寄生参数(interconnect parasitics)所指导的延迟模型下,联合选择逻辑切割(logic cuts)、信号极性(signal polarities)和库单元(library cells)。在离散优化产生具有相似建模时序和不同结构选择的替代实现之前,一个连续松弛(continuous relaxation)用于过滤搜索空间。这些实现通过合法化(legalization)、基于布线的寄生参数估计和时序分析进行重建和评估。经物理验证的改进被纳入设计,更新的上下文指导后续搜索。该框架提供了一种系统化的方式,在考虑与现有布局交互的同时,重新审视局部逻辑实现。

英文摘要

The timing behavior of a mapped circuit depends on both its logic implementation and the physical environment in which that implementation is realized. Revisiting mapping decisions after placement therefore requires a search procedure that accounts for surrounding timing constraints, fanout loads, and interconnect effects. We study local remapping in this setting and develop a framework that couples discrete mapping search with physical implementation feedback. Timing-critical regions are isolated through bounded windows whose interfaces retain the context of the surrounding circuit. Within each window, a mixed-integer formulation jointly selects logic cuts, signal polarities, and library cells under a delay model informed by estimated locations and interconnect parasitics. A continuous relaxation filters the search space before discrete optimization produces alternative implementations with similar modeled timing and different structural choices. These implementations are reconstructed and assessed through legalization, routing-based parasitic estimation, and timing analysis. Physically validated improvements are incorporated into the design, and the updated context guides subsequent searches. The framework provides a systematic way to revisit local logic implementations while accounting for their interaction with an existing placement.

论文原文

arXiv 摘要页 · PDF 原文 · HTML 原文

↑