U-Sonic：130 nm RISC-V SoC中的开源8通道超声发射IP
U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
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中文总结 AI 辅助
本文提出U-Sonic，一个集成于32位RISC-V SoC的开源8通道超声发射IP，支持可编程激励和同步控制，在130 nm工艺下实现14.9 kGE面积，并开源发布。
中文摘要 AI 辅助
微型化超声（US）探头需要跨多个阵元的可编程且同步的发射（TX）激励，而现有的紧凑型平台通常依赖有限的微控制器（MCU）脉冲发生器或闭源的固定功能脉冲器设备。我们提出了U-Sonic，一个集成到32位RISC-V片上系统（SoC）中的开源数字超声发射外设。所实现的SoC集成了8个脉冲器核心，而参数化架构支持多达16个通道。每个核心生成单音或双音突发，具有可编程的周期、占空比、脉冲数、极性和空闲电平，并带有可选的用于主动阻尼的反向停止脉冲。共享的内存映射开放总线接口（OBI）能够同步启动和停止任意通道子集，并支持复合双极、门控和三电平激励方案。功能正确性在Verilator中针对Python黄金模型在4379个检查周期内（涵盖定向和随机配置）进行了验证，并在Terasic DE10-Lite现场可编程门阵列（FPGA）上得到确认。该设计在IHP 130 nm工艺下进行了综合和布局布线。布局后面积以千门等效（kGE）计，按每通道1.65 kGE加1.66 kGE缩放。8通道实例占用14.9 kGE，相当于104 kGE SoC的约14.3%。寄存器传输级（RTL）、寄存器描述、验证配套和软件支持均以开源形式发布。
英文摘要
Miniaturized ultrasound (US) probes require programmable and synchronized transmit (TX) excitation across multiple elements, while existing compact platforms often rely on limited microcontroller (MCU) pulse generators or closed-source fixed-function pulser devices. We present U-Sonic, an open-source digital US TX peripheral integrated into a 32-bit RISC-V system-on-chip (SoC). The implemented SoC integrates 8 pulser cores, while the parameterized architecture supports up to 16 channels. Each core generates single- or dual-tone bursts with programmable period, duty cycle, pulse count, polarity, and idle level, together with optional inverted stop pulses for active damping. A shared memory-mapped Open Bus Interface (OBI) enables synchronous start and stop of arbitrary channel subsets and supports composite bipolar, gated, and three-level excitation schemes. Functional correctness was verified in Verilator against a Python golden model over 4379 checked cycles across directed and randomized configurations, and confirmed on a Terasic DE10-Lite field-programmable gate array (FPGA). The design was synthesized and placed-and-routed in IHP 130 nm. The post-layout area in kilo gate equivalents (kGE), scales as 1.65 kGE plus 1.66 kGE per channel. The 8-channel instance occupies 14.9 kGE, corresponding to approximately 14.3% of the 104 kGE SoC. The register-transfer level (RTL), register descriptions, verification collateral, and software support are released as open source.
