发表机构
Universitat Politècnica de Catalunya; Universitat Politècnica de València（加泰罗尼亚理工大学; 瓦伦西亚理工大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
提出路由感知的量子电路剪枝策略，通过比较门计算贡献与保真度成本移除冗余双量子比特门，在NISQ和容错架构中实现门数减少48.6%和保真度提升47.7%。
AI 中文摘要
我们提出了一种面向路由感知的量子电路剪枝策略，该策略选择性地移除参数化双量子比特门，这些门的计算贡献被其执行保真度成本所抵消，并在含噪中等规模量子（NISQ）和容错量子计算（FTQC）架构中对其进行评估。电路中的每个双量子比特门通过比较省略该门的架构无关保真度成本下界与每种设置中硬件特定的路由执行成本模型来进行评估。我们还提供了剪枝边界作为旋转角度、量子比特距离和硬件噪声函数的解析表征。在基准电路上的模拟表明，在NISQ体制下，门数量最多减少48.6%，保真度最多提升47.7%，而对FT硬件的可行性分析表明，剪枝预计在一系列代码距离和物理错误率下仍保持相关性。这些结果确立了路由感知剪枝作为跨量子计算栈的实用且统一的编译策略。
英文摘要
We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.
