Zephyr：一种利用稀疏感知灵活FPGA处理单元阵列的脉冲神经网络高效音频降噪系统
Zephyr: An Efficient Audio Denoising System Using Spiking Neural Networks Enabled With A Sparsity-Aware Flexible FPGA PE Array
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中文总结 AI 辅助
针对边缘设备音频降噪的功耗问题，提出基于脉冲神经网络的Zephyr系统，通过量化感知训练和激活简化实现约28倍功耗降低，并设计稀疏感知FPGA阵列，在PYNQ-Z1上达到0.727实时因子。
中文摘要 AI 辅助
在本工作中，我们着眼于神经形态计算，以解决音频降噪神经网络在智能手机、无线耳机和助听器等边缘设备上面临的功耗问题。脉冲神经网络（SNNs）因其高激活稀疏性和低复杂度而有望解决此问题，然而许多最先进的SNN需要支持混合操作的硬件才能完全执行推理。为解决此问题，我们将最先进的音频降噪神经网络Spiking-FullSubNet转换为硬件友好版本，通过量化感知训练（QAT）和激活函数简化，在45nm工艺节点上为定制数字硬件计算时，功耗可降低约28倍，达到每32ms音频帧52.9nJ。随后，我们提出了一种数字电路，通过稀疏感知的灵活处理单元阵列，能够对Spiking-FullSubNet的异构计算负载执行推理，并在PYNQ-Z1 FPGA上验证了该电路，在100MHz频率下实现了0.727的实时因子。
英文摘要
In this work we look to neuromorphic computing to solve the power consumption problem that audio denoising neural networks face on edge devices like smartphones, wireless headphones and hearing aids. Spiking neural networks (SNNs) have the potential to solve this problem due to their high activation sparsity and low complexity, however many SOTA SNNs require hardware that supports a mixture of operations to be able to fully perform inference. To solve this problem, we convert SOTA audio denoising neural network Spiking-FullSubNet to a hardware friendly version showing that via QAT and activation function simplification we can achieve $\approx28\times$ improvement in power consumption to 52.9nJ per 32ms audio frame when calculated for custom digital hardware in a 45nm process node. We then propose a digital circuit which by means of a sparsity-aware flexible PE array can perform inference of the heterogeneous compute load of Spiking-FullSubNet, and validate this circuit on a PYNQ-Z1 FPGA achieving a real-time factor of 0.727 at 100MHz.
发表机构
- National Tsing Hua University（国立清华大学）
机构由 AI 辅助整理，请以论文原文为准。
