高级HDL中的低级优化：是否有益？
Low-level optimizations in high-level HDLs: Is there a benefit?
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- TU Clausthal（Clausthal工业大学）
- Technical University of Denmark（丹麦技术大学）
机构由 AI 辅助整理，请以论文原文为准。
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中文总结 AI 辅助
本文通过16种配置的MAC单元实验，比较了高级HDL Clash与低级优化及Verilog在ASIC设计中的面积影响，发现高级构造影响可忽略，但Clash存在固有开销。
中文摘要 AI 辅助
本文探讨了函数式编程在专用集成电路（ASIC）设计中的适用性。我们研究了使用高级、抽象的硬件描述语言（HDL）特性设计ASIC与采用低级优化对综合电路面积的影响。目的是确定使用低级优化是否有益，如果有益，是否值得增加实现工作量。为开展研究，我们使用函数式HDL Clash实现了16种不同配置的无符号位串行乘累加（MAC）单元。我们既使用了低级位操作技术，也使用了Clash的高级构造进行电路设计。实验评估表明，Clash的某些高级构造对最终电路尺寸的影响可忽略不计，这表明使用函数式编程的全部功能是硬件设计的可行方法。为了评估所用HDL本身的影响，我们还用Verilog实现了MAC的版本。实验清楚地表明，与经验丰富的工程师编写的Verilog代码相比，使用Clash似乎存在固有的开销。
英文摘要
This paper explores the applicability of functional programming to the design of Application-specific Integrated Circuits (ASICs). We investigate the impact of designing ASICs using high-level, abstract Hardware Description Language (HDL) features versus employing low-level optimizations on the area of the synthesized circuits. The aim is to determine whether using low-level optimizations is beneficial and, if so, whether it is worth the added implementation effort. To carry out the investigation, we implement an unsigned bit-serial multiply-accumulate (MAC) unit in 16 different configurations using the functional HDL Clash. We make use of both low-level bit-manipulation techniques as well as Clash's high-level constructs for circuit design. The experimental evaluation shows that some high-level constructs of Clash have negligible influence on the resulting circuit size, suggesting that using the full power of functional programming is a viable approach to hardware design. To evaluate the impact of the used HDL itself, we also implemented versions of the MAC in Verilog. The experiments clearly show that there seems to be an inherent overhead in using Clash compared to Verilog code written by a seasoned engineer.
