发表机构
Hewlett Packard Labs, Hewlett Packard Enterprise; Department of Electrical and Computer Engineering, Texas A&M University（惠普实验室，惠普企业; 德克萨斯农工大学电气与计算机工程系）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文针对200 Gb/s以上硅微环调制器，分析器件物理与工作点，提出协同设计方法及紧凑模型，用于扩展和横向扩展光I/O，以降低DSP功耗。
AI 中文摘要
光输入/输出（I/O）支持人工智能（AI）系统中处理器之间的高带宽通信。耗尽型硅微环调制器具有紧凑的尺寸、波分复用能力以及每比特飞焦量级的结开关能量。然而，随着通道速率提升至200 Gb/s及以上，执行均衡和前向纠错的数字信号处理器（DSP）可能消耗高达光模块功率的一半。我们分析了硅微环调制器的结和腔物理，将调制效率、电容、光学损耗和耦合与带宽及驱动要求相关联，以指导每通道200 Gb/s以上的器件优化。通过区分最大静态斜率、静态和动态OMA以及增益-带宽积（GBW），研究了激光失谐和最佳工作点，包括结RC响应的影响。讨论了光学自热、光载流子和偏置网络电压降对谐振的影响，以及DWDM阵列中的加热器调谐和波长分配。根据所需的热失谐、链路预算导出的光功率和假设的热参数计算冷谐振设计点，并将加热器余量和启动采集作为设计约束。使用耦合电、光和热动力学的紧凑模型评估PAM4眼图，并提供模型核心的Verilog-A实现用于电路级仿真。
英文摘要
Optical input/output (I/O) supports high-bandwidth communication between processors in artificial intelligence (AI) systems. Depletion-mode silicon microring modulators offer compact footprints, wavelength multiplexing and femtojoule-scale junction switching energy per bit. However, as lane rates increase to 200~Gb/s and beyond, a digital signal processor (DSP) performing equalization and forward-error correction can consume up to half of the optical module power. We analyze the junction and cavity physics of silicon microring modulators, relating modulation efficiency, capacitance, optical loss and coupling to bandwidth and drive requirements to guide device optimization above 200~Gb/s per lane. Laser detuning and optimal operating points are examined by distinguishing maximum static slope, static and dynamic OMA, and gain--bandwidth product (GBW), including the influence of the junction RC response. The effects of optical self-heating, photocarriers and bias-network voltage droop on the resonance are discussed together with heater tuning and wavelength assignment in DWDM arrays. Cold-resonance design points are calculated from the required hot detuning, link-budget-derived optical power and assumed thermal parameters, with heater reserve and startup acquisition included as design constraints. A compact model of the coupled electrical, optical and thermal dynamics is used to evaluate PAM4 eye diagrams, and a Verilog-A implementation of the model core is provided for circuit-level simulation.
