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arXiv 2609.35624physics.ins-detquant-ph

埋入商用CMOS工艺中的超导纳米线的电热行为

Electrothermal behavior of superconducting nanowires buried in a commercial CMOS process

发表机构伊利诺伊大学芝加哥分校 · 阿贡国家实验室 · 芝加哥大学
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  • University of Illinois Chicago(伊利诺伊大学芝加哥分校)
  • Argonne National Laboratory(阿贡国家实验室)
  • University of Chicago(芝加哥大学)
  • Quantum Motion(量子运动)

机构由 AI 辅助整理,请以论文原文为准。

Mohamed Gharib, Leonid Popryho, Salma Abdelzaher, Tejas Guruswamy, Tomas Polakovic, Umeshkumar Patel, Orlando Quaranta, Thomas Cecil, Clarence Chang, Yu-Sheng C… 展开作者

Mohamed Gharib, Leonid Popryho, Salma Abdelzaher, Tejas Guruswamy, Tomas Polakovic, Umeshkumar Patel, Orlando Quaranta, Thomas Cecil, Clarence Chang, Yu-Sheng Chen, Thomas H. Swift, Grayson M. Noah, Alberto Gomez-Saiz, John J. L. Morton, M. Fernando Gonzalez-Zalba, Antonino Miceli, Inna Partin-Vaisband

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中文总结 AI 辅助

本研究通过测量埋入22nm FD-SOI CMOS工艺的TiN纳米线的电流-电压特性,揭示了其强滞回电热行为,并建立了包含纵向传导与界面冷却的双通道热模型,准确描述了回复电流对长度和温度的依赖。

中文摘要 AI 辅助

商用CMOS工艺自带的超导薄膜使得超导器件(高动态电感元件和纳米线探测器)能够与低温CMOS共同集成在同一单片上。此类薄膜埋置于前端工艺层中,位于后端金属叠层之下,这种环境可能会使自热热点猝灭。本文报道了在22 nm FD-SOI工艺的多晶硅电阻层中制备的氮化钛(TiN)纳米线的电流-电压特性,并将实测的回复电流与纵向传导至接触点的热模型及界面声子冷却至叠层的热模型进行了比较。这些纳米线表现出强烈的滞回特性,开关电流与回复电流之比I_sw/I_r为7.4-9.8,能够维持正常态热点。对于两根长度ell = 50微米、宽度W分别为0.50和1.00微米的纳米线,在浴温度T_b = 0.15-1.19 K范围内,I_r符合界面形式(T_hs^n - T_b^n)^(1/2),其中n = 4(T_hs为有效热点温度),且与(T_hs - T_b)^(1/2)的常数κ纵向传导极限强烈不符;自由指数拟合给出n约为4.8-5.0。有效冷却系数Sigma_K = 7.9(3) W/(m^2 K^4)描述了数据:比单个清洁界面的声学(漫反射)失配值低31(21)倍,比先前报道的最低可比纳米线系数低约12倍。基于模型的薄膜热导率为κ约为20 mW/(m K)。在长度ell = 1-50微米范围内,I_r既不符合纯纵向传导的ell^(-1)规律,也不符合纯界面冷却的ell^0规律;双通道模型再现了I_r(ell)的变化,预测交叉长度ell*约为3.5微米,其与Sigma_K和κ的关系符合O(1)前置因子。

英文摘要

Superconducting films native to a commercial CMOS process enable co-integration of superconducting devices (high-kinetic-inductance elements and nanowire detectors) with cryogenic CMOS on one monolithic die. Such films are buried in the front-end-of-line, beneath the back-end-of-line metal stack, an environment that might quench a self-heated hot spot. Current-voltage characteristics are reported for titanium nitride (TiN) nanowires in the polycrystalline-silicon resistor layer of a 22 nm FD-SOI process, and measured retrapping currents are compared with thermal models for longitudinal conduction to the contacts and interfacial phonon cooling into the stack. The wires are strongly hysteretic, with switching-to-retrapping current ratios I_sw/I_r of 7.4-9.8, sustaining a normal hot spot. For two wires of length ell = 50 micrometers and widths W = 0.50 and 1.00 micrometers, over bath temperatures T_b = 0.15-1.19 K, I_r follows the interfacial form (T_hs^n - T_b^n)^(1/2) with n = 4 (T_hs, the effective hot-spot temperature), and is strongly inconsistent with the (T_hs - T_b)^(1/2) constant-kappa longitudinal-conduction limit; free-exponent fits give n = approximately 4.8-5.0. An effective cooling coefficient Sigma_K = 7.9(3) W/(m^2 K^4) describes the data: 31(21) times below the acoustic- (diffuse-) mismatch value for a single clean interface, and approximately 12 times below the lowest previously reported comparable nanowire coefficient. The model-based film thermal conductivity is kappa = approximately 20 mW/(m K). Across lengths ell = 1-50 micrometers, I_r matches neither ell^(-1) of pure longitudinal conduction nor ell^0 of pure interfacial cooling; a two-channel model reproduces I_r(ell) with crossover length ell* = approximately 3.5 micrometers predicted, to an O(1) prefactor, from Sigma_K and kappa.

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