用于托卡马克中兆赫兹诊断边缘AI与等离子体控制系统集成调试的分组级数字硬件孪生
A packet-level digital hardware twin for commissioning megahertz diagnostic edge AI and plasma control system integration in tokamaks
- University of Wisconsin–Madison（威斯康星大学麦迪逊分校）
- SLAC National Accelerator Laboratory（SLAC国家加速器实验室）
- General Atomics（通用原子公司）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
本文提出一种分组级数字硬件孪生，用于模拟托卡马克兆赫兹诊断边缘AI系统，以测试诊断到控制接口及故障安全行为，实现91.6微秒中位延迟。
AI中文摘要：
高带宽等离子体诊断日益为用于实时托卡马克控制的机器学习和信号处理算法提供输入，但由于其采样率，从诊断采样到控制系统交接的完整路径难以调试。我们为兆赫兹诊断边缘AI架构开发了一个分组级数字硬件孪生。该模拟器表示一个嵌入在96通道双载波采集系统中的64通道、1 MHz束发射光谱（BES）诊断，该系统包含两个带有SPAD0采样计数器的48通道流、10 GbE硬件UDP传输、分组丢失和网络抖动、FPGA解析和双载波对齐、因果预处理和边缘推理、一个紧凑的以太网结果分组、接收端共享状态，以及一个1 kHz类PCS控制周期。生成二进制UDP负载和PCAP文件，而不是仅在阵列级别模拟传输。在每分组20个样本的基线设置下，每个载波每秒生成50,000个分组，用户负载为每秒100 MB。一次110毫秒的参考运行产生11,000个HUDP分组；一个故意丢弃的20样本分组被采样计数器连续性逻辑检测到，并使两个重叠的128样本推理窗口失效，而不会进行静默插值。对于有效窗口，配置的工程延迟模型给出中位最后输入到共享内存延迟为91.6微秒，第99百分位为108.1微秒。一个单独的操作系统回环测试通过UDP接收器将二进制FPGA结果数据报发送到POSIX共享内存，并保持20/20分组的序列和CRC完整性。交互式GUI界面暴露时序、分组化、网络故障、推理阈值和控制状态检查。该框架为测试诊断到加速器接口和部署在聚变装置上的故障安全行为提供了一个可复现的环境。
英文摘要：
High-bandwidth plasma diagnostics increasingly provide inputs to machine learning and signal-processing algorithms intended for real-time tokamak control, but the complete path from diagnostic sampling to control-system handoff is difficult to commission because of their sampling rates. We develop a packet-level digital hardware twin for the megahertz diagnostic edge-AI architecture. The simulator represents a 64-channel, 1 MHz beam emission spectroscopy (BES) diagnostic embedded in a 96-channel dual-carrier acquisition system, two 48-channel streams with SPAD0 sample counters, 10 GbE Hardware UDP transport, packet loss and network jitter, FPGA parsing and dual-carrier alignment, causal preprocessing and edge inference, a compact Ethernet result packet, receiver-side shared state, and a 1 kHz PCS-like control cycle. Binary UDP payloads and PCAP files are generated rather than emulating transport only at the array level. With a baseline of 20 samples per packet, each carrier generates 50,000 packets s$^{-1}$ and 100 MB s$^{-1}$ of user payload. A 110 ms reference run produces 11,000 HUDP packets; an intentionally dropped 20-sample packet is detected by the sample-counter continuity logic and invalidates the two overlapping 128-sample inference windows without silent interpolation. For valid windows, the configured engineering latency model gives a median last-input-to-shared-memory latency of 91.6 us and a 99th percentile of 108.1 us. A separate operating-system loopback test sends binary FPGA-result datagrams through a UDP receiver into POSIX shared memory and preserves packet sequence and CRC for 20/20 packets. Interactive GUI interfaces expose timing, packetization, network faults, inference thresholds, and control-state inspection. The framework provides a reproducible environment for testing diagnostic-to-accelerator interfaces and fail-safe behavior for deployment on fusion devices.
