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MQSS-Selector:用于MLIR编译管线的强化学习引导的Pass选择

MQSS-Selector: RL-Guided Pass Selection for an MLIR Compilation Pipeline

Andre Youssefi, Ercüment Kaya, Minh Chung, Jorge Echavarria, Laura B. Schulz, Martin Schulz

arXiv 2609.30104首次发表:更新:

发表机构

Leibniz Supercomputing Centre (LRZ); Technical University of Munich (TUM); Munich Quantum Valley (MQV); Argonne National Laboratory (ANL)(莱布尼茨超级计算中心; 慕尼黑工业大学; 慕尼黑量子谷; 阿贡国家实验室)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

本文提出MQSS-Selector,一个基于强化学习与深度学习的统一选择器,将量子编译中的设备选择、Pass优化与调度整合,以同时优化保真度、编译时间和调度延迟。

AI 中文摘要

高性能计算(HPC)和量子计算(QC)系统正日益趋向于统一的高性能计算-量子计算(HPCQC)基础设施,这一趋势源于连接经典与量子工作流的日益增长的需求,其影响涉及系统栈的所有层面,从硬件到编译器与运行时,直至应用程序。然而,当今的量子计算设备仍处于含噪声中等规模量子(NISQ)时代,易出错且资源受限,因此需要专门的优化和拓扑映射以达到足够的保真度。这特别强调了在整体量子软件栈中进行恰当的编译与优化的重要性。许多现有栈仍然碎片化,设备选择、编译器Pass优化和作业队列调度由独立组件分别负责。本文提出一个统一的、基于学习的选择器,将这些不同阶段整合到一个连贯的框架中。我们提出的选择器方案利用强化学习和深度学习模型,可扩展以同时优化多个目标——如保真度、编译时间和调度延迟——同时动态适应电路特征和设备条件。

英文摘要

High Performance Computing (HPC) and Quantum Computing (QC) systems are increasingly converging towards unified High Performance Computing-Quantum Computing (HPCQC) infrastructures, driven by a growing need to bridge classical and quantum workflows, which affects all levels of the system stack, from the hardware to compilers and runtimes, all the way to applications. However, today's QC devices are still in the Noisy Intermediate-Scale Quantum (NISQ) era, are error-prone and resource-limited, and therefore require specialized optimizations and topology mappings to achieve sufficient fidelity. This places special emphasis on proper compilation and optimization within the overall quantum software stack. Many existing stacks remain fragmented, with separate components responsible for device selection, compiler-pass optimization, and job queue scheduling. This paper proposes a unified, learning-based selector that integrates these disparate stages into a cohesive framework. Our proposed selector scheme leverages reinforcement learning and deep learning models that can be extended to simultaneously optimize multiple objectives -- such as fidelity, compilation time, and scheduling latency -- while dynamically adapting to circuit characteristics and device conditions.

Comments11 pages, 5 figures, 1 table

论文原文

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