发表机构
ETH Zurich（苏黎世联邦理工学院）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
本文介绍苏黎世联邦理工学院研究生课程VLSI 5中，19名学生开发的EZ130 8T开源标准单元库，相比IHP SG13G2库在八个基准上显著减少面积，并在8x8矩阵乘法器中降低35%面积和39%能耗。
AI 中文摘要
标准单元库构成了晶体管级电路设计与自动化数字设计流程之间的关键接口，然而在数字VLSI课程中，其设计和特性化很少被深入涵盖。本文介绍了VLSI 5，这是苏黎世联邦理工学院（ETH Zurich）的一门研究生课程，学生在该课程中使用IHP的开源130nm SG13G2工艺设计套件设计、布局、特性化并集成自己的标准单元。在首次课程中，19名学生开发了EZ130 8T，这是一个包含220个单元的开源八轨标准单元库。我们使用八个综合基准评估了连续版本的库，结果表明，与SG13G2库相比，EZ130 8T在竞争性时序下实现了显著的面积缩减。对于布局后的8x8矩阵向量乘法器，EZ130 8T将单元面积减少了35%，能耗减少了39%，同时保持了几乎相同的时钟周期。该库已被苏黎世联邦理工学院的其他VLSI课程采用，使得完全由学生设计到晶体管级的芯片成为可能。
英文摘要
Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP's open-source 130nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8x8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.
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