忆阻器因子化低秩近似计算方案的功率-MSE权衡
Power-MSE trade-off of Factorized Low-rank Approximated Computation Scheme with Memristors
- University of Melbourne（墨尔本大学）
- University of Toronto（多伦多大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
本研究扩展因子化低秩近似方案（FLAS）以支持可调电导缩放，推导闭式MSE与功率表达式，建立功率-MSE权衡框架，数值验证其在忆阻器VMM中的优势。
AI中文摘要：
忆阻器交叉阵列支持模拟向量-矩阵乘法（VMM），这在机器学习应用中具有前景。将矩阵条目缩放至较低的忆阻器电导水平可降低功耗，但会增加忆阻器编程噪声对VMM精度的影响。为探究低秩分解如何改善这一权衡，我们将先前提出的因子化低秩近似方案（FLAS）扩展以支持可调电导缩放。随后，我们推导了FLAS和基线VMM的闭式均方误差（MSE）和功率表达式。基于这些表达式，我们建立了一个解析性的功率-MSE权衡框架，以捕捉在忆阻器数量和电导缩放界限约束下，近似秩、复制分配和电导缩放的耦合效应。数值结果展示了FLAS在不同奇异值谱矩阵上的功率-MSE优势。功率分解解释了跨阻放大器（TIA）反馈电阻如何影响这一优势。
英文摘要：
Memristor crossbars enable analog vector-matrix multiplication (VMM) which is promising for machine learning applications. Scaling matrix entries to lower memristor conductance levels reduces power consumption but increases the impact of memristor programming noise on VMM accuracy. To investigate how low-rank factorization can improve this trade-off, we extend the previously proposed factorized low-rank approximation scheme (FLAS) to support adjustable conductance scaling. We then derive closed-form MSE and power expressions for both FLAS and baseline VMM. Based on these expressions, we establish an analytical power-MSE trade-off framework to capture the coupled effects of approximation rank, replication allocation, and conductance scaling under constraints on memristor count and conductance scaling bounds. Numerical results demonstrate FLAS's power-MSE advantage across matrices with different singular value spectra. The power decomposition explains how TIA feedback resistance affect this advantage.
