PANEM：一种启发式延迟模型
PANEM: A Heuristic Latency Model
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中文总结 AI 辅助
PANEM提出轻量级事件驱动启发式延迟模型，将带宽-延迟数据转为动态响应，在单核流程中实现竞争感知延迟，避免固定延迟偏差，提升云负载下核心资源决策。
中文摘要 AI 辅助
准确的硅前内存建模对于在云级多核处理器上实现有意义的工作负载表示至关重要。现有选项在保真度和速度之间造成了糟糕的权衡：固定延迟模型速度快但具有误导性，而周期精确的DRAM模型成本高昂且难以扩展到大型研究空间或单核环境。本文介绍了PANEM，一种轻量级事件驱动启发式模型，已在Ampere Computing指导了四代商用服务器核心的开发。PANEM将带宽-延迟表征数据转换为动态的请求字节/延迟响应，使未命中延迟能够适应模拟期间的瞬态需求、排队压力和读/写混合。集成到具有可配置系统负载假设的单核流程中，PANEM在不牺牲吞吐量的情况下实现了现实的带宽约束和竞争感知延迟行为。在广泛的云工作负载轨迹套件中，PANEM避免了固定延迟基线的乐观和悲观偏差，为预取和动态节流研究提供了更可靠的结论，并实质性改善了核心资源规模决策。这些结果表明，校准的竞争感知抽象可以在与固定延迟模型相似的模拟成本下，为工业设计空间探索提供实用的预测价值。
英文摘要
Accurate pre-silicon memory modeling is essential for achieving meaningful representation of workloads on cloud-class many-core processors. Existing options force a poor tradeoff between fidelity and speed: fixed-latency models are fast but misleading, while cycle-accurate DRAM models are costly and difficult to scale across large study spaces or onto single-core environments. This paper presents PANEM, a lightweight event-driven heuristic model that has guided four generations of commercial server-core development at Ampere Computing. PANEM converts bandwidth-latency characterization data into a dynamic request-bytes/latency response, allowing miss latency to adapt to transient demand, queuing pressure, and read/write mix during simulation. Integrated into a single-core flow with configurable system-loading assumptions, PANEM enables realistic bandwidth constraints and contention-aware latency behavior without sacrificing throughput. Across a broad cloud workload trace suite, PANEM avoids the optimistic and pessimistic biases of fixed-latency baselines, yields more reliable conclusions for prefetching and dynamic throttling studies, and materially improves core-resource sizing decisions. These results show that a calibrated, contention-aware abstraction can deliver practical predictive value for industrial design-space exploration at simulation costs similar to fixed-latency models.
发表机构
- Ampere Computing（安谋科技）
机构由 AI 辅助整理，请以论文原文为准。
