发表机构
Politecnico di Milano（米兰理工大学）
机构由 AI 辅助整理，请以论文原文为准。AI 中文总结
Toki是首个开源软硬件框架，通过联合RISC-V软核工作负载与PCIe主机DMA流量，在AMD Alveo U55C上剖析HBM性能，揭示计算核心组织、访问模式及争用对性能的影响。
AI 中文摘要
可编程RISC-V软核在数据中心场景中正变得越来越普遍，这使得设计在带有HBM存储器的FPGA芯片上高效部署这些软核的系统变得至关重要。Toki以开源形式发布，是首个能够剖析FPGA加速卡上HBM性能的硬件-软件框架，它通过联合考虑(i)在FPGA上实例化的RISC-V软核上执行工作负载，以及(ii)通过PCIe上的DMA从主机系统注入内存流量，提供了仅靠合成流量生成器无法获得的洞察。大量实验针对AMD Alveo U55C卡，部署了多达60个RISC-V计算核心，并通过真实应用和具有用户自定义访问模式的微基准测试对其HBM2存储器施加压力。结果表明，Toki能够有效剖析计算核心的组织方式、工作负载的内存访问模式、数据局部性、内存控制器上的争用以及主机流量对HBM性能的影响。
英文摘要
Programmable RISC-V soft cores are becoming more widespread in data-center scenarios, making it crucial to design efficient systems that deploy them on FPGA chips with HBM memory. Toki, released as open source, is the first hardware-software framework that enables profiling the performance of HBM on FPGA accelerator cards by jointly considering (i) the execution of workloads on RISC-V soft cores instantiated on the FPGA and (ii) the injection of memory traffic from the host system via DMA over PCIe, providing insights that cannot be obtained with synthetic traffic generators alone. Extensive experiments target an AMD Alveo U55C card, deploying up to 60 RISC-V compute cores and stressing its HBM2 memory through real-world applications and microbenchmarks with user-defined access patterns. Results showcase how Toki can effectively profile the impact on HBM performance of the compute cores' organization, the workload's memory access patterns, data locality, contention over the memory controllers, and host traffic.
CommentsPresented at the 63rd ACM/IEEE Design Automation Conference (DAC '26), July 26-29, 2026, Long Beach, CA, USA; 7 pages, 7 figures, 2 tables
